参数资料
型号: GT-48001A
厂商: Galileo Technology Services, LLC
英文描述: Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器)
中文描述: 交换式以太网控制器10BaseX(10BaseX交换式快速以太网控制器)
文件页数: 51/101页
文件大小: 1235K
代理商: GT-48001A
GT-48001A Switched Ethernet Controller
Revision 1.6
53
12.12.5 Synchronous Mode
Synchronous mode allows an external device to drive or receive an NRZ encoded bitstream directly to/from the GT-
48001A. The interface is similar to the MII interface defined for 100Mbps Fast Ethernet. This mode is particularly useful
when interfacing to Motorola embedded controllers such as the MPC860 and 68360 family.
NOTICE: To use Sync Mode, all ports must be configured for Sync Mode. See Section 18.
Figure 9 illustrates the relationship that must be observed for the SynClk20 and SynClk10 clock inputs when the GT-
48001A is in Synchronous Mode. Notice that the rising edge of SynClk10 should match the falling edge of SynClk20.
Figure 9: SynClk20 Relationship to SynClk10
Table 30: Synchronous Ethernet Interface Pin Descriptions
Pi n Na m e
I/ O
Sy n c
Mo de
Fu n c t i on a l it y
SClk
I
SynClk20
20 MHz Clock.
RxD
I
RxD*
Receive Data: Active LOW. The decoded NRZ data input.
Synchronous to SynClk10’s rising edge.
RxLP
I
Coll*
Collision Detect: Active LOW. Synchronous to SynClk20’s ris-
ing edge. This pin must be pulled HIGH for full duplex opera-
tion.
CrS
I
RxDV*
Receive Data Valid: Active LOW. Indicates that the data
present on the RxD* is valid. Synchronous to SynClk10’s ris-
ing edge.
Pol[0]
I
SynClk10
10 MHz transmit/receive clock. This clock serves as the
receive and transmit clock for all 8 ports.
There is no separate
clock for each port.
Pol[7:1]
O
NC
Do not drive this pin.
TxD
O
TxD*
Transmit Data: Active LOW. The NRZ transmitted data output.
Driven from SynClk10’s falling edge.
TxDDel
O
NC
Do not drive this pin.
TxEn
O
TxEn*
Transmit Enable: Active LOW. Indicates that the data present
on the TxD* is valid. Driven from SynClk10’s falling edge.
SynClk20
SynClk10
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