
GT-48001A Switched Ethernet Controller
60
Revision 1.6
Setting this bit should also generate a processor interrupt. The Interrupt Cause register may be read to determine the
state of the Ease_Registers, and may be written to clear the interrupt condition described above. It is possible for the
CPU to mask the interrupt condition as well as clear the interrupt condition. The GT-48001A implements a mask bit in
the Interrupt Mask register for each EASE status bit in the Interrupt Cause register. Masking and clearing the interrupts
are executed in a way that is consistent with the other interrupts supported by the GT-48001A.
EASE Interrupt Caus e Re gi s ter, Offset: 0x050
EASE Interrupt Ma sk Regi s te r, Offse t: 0x05 4
14.5
Sampled Packet Indication
Sampled packets are copied into the CPU’s receive buffers using the same mechanism as normal receive packets. The
only difference, from the CPU’s point of view, is that the GT-48001A will put an indication in the first word of the receive
buffer which identifies the packet as a sample. The sample indication bits specify which ports on the particular GT-
48001A the sample is associated with. It is possible for a single sample to be associated with more than one port at a
time. For example, a broadcast packet flooded to all ports may be sampled on several ports if each of their skip counters
had previously been decremented to zero.
Each GT-48001A device operates independently, so it is possible for the CPU to receive the same sample from different
GT-48001A devices. For example, a broadcast packet flooded to all ports in the system may be sampled by several
GT-48001As at the same time. Each sample will result in a separate copy of the packet being sent to the CPU. It is also
possible to sample a packet which would normally be received by the CPU. In this case, only a single copy of the packet
can be sent to the CPU. The CPU should be responsible for determining if a sampled packet should also be accepted
as a normal receive packet. In the case where a normally received packet is also a sample from multiple GT-48001A
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
0
EaseReg0Empty
Ease_Register of port 0 is empty
0x0
1
EaseReg1Empty
Ease_Register of port 1 is empty
0x0
2
EaseReg2Empty
Ease_Register of port 2 is empty
0x0
3
EaseReg3Empty
Ease_Register of port 3 is empty
0x0
4
EaseReg4Empty
Ease_Register of port 4 is empty
0x0
5
EaseReg5Empty
Ease_Register of port 5 is empty
0x0
6
EaseReg6Empty
Ease_Register of port 6 is empty
0x0
7
EaseReg7Empty
Ease_Register of port 7 is empty
0x0
8
ErrorSASent
Error_Source message sent to CPU
0x0
[31:9]
n/a
Always write with 0x0
0x0
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
8:0
MaskBits
Mask the CPU interrupt line for the appropriate bits in the Interrupt
Cause register.
0x0
[31:9]
n/a
Always write with 0x0
0x0