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| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 27/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
31
10.
GalNet Messaging Protocol
The GalNet Messaging Protocol is comprised of the messages passed over the PCI bus between
GalNet family members
a GalNet family member and a CPU
.The messages are encoded in both the address and the data phases of the PCI transfers. Five groups of messages
that are currently defined: NEW_ADDRESS, BUFFER_REQUEST, START_OF_PACKET, PACKET_TRANSFER, and
END_OF_PACKET.
GalNet messages are write-only (request/response). For example, a GalNet device that needs to transfer data to
another GalNet chip starts the transfer by requesting a buffer (BUFFER_REQUEST) from the target. The target
responds with an address to which the packet should be transferred to (START_OF_PACKET).
The GalNet messaging protocol allows messages to be interleaved. For example, a device may send out multiple
BUFFER_REQUEST messages to other devices before receiving a START_OF_PACKET message reply.
Write only messaging was used since it better utilizes PCI bus bandwidth. Reads on the PCI bus tend to stall the bus,
and the reading device thereby degrading overall system performance.
Please note that there are subtle differences in the GalNet message format when transferring messages between
devices (Section 10.2) and between a device and a CPU (Section 10.3).
10.1
GalNet Protocol Region
All GalNet devices in a system must reside within a single 128Mbyte region in the PCI memory address space known
as the GalNet Protocol Region (GPR). The base address of the GPR is set in bits 31:27 of the DRAM/Internal Base
Address Register at offset 0x10 in the GT-48001A’s PCI configuration header.1 All GalNet devices in a system MUST
have the same value in this field. GalNet devices default to a value of ‘00001’ in the GPR bits following RESET.
Each GalNet device in the system occupies a separate 4Mbyte “slice” of the GalNet Protocol Region. This “slice” is
decoded by the Device Number field in the DRAM/Internal Base Address Register (bits 26:22). The individual device’s
address space is further divided by the DRAM/Register bit (bit 21). This bit determines whether an access to a target
device is directed to the DRAM array or to the registers.
1. Offset 0x10 in the PCI configuration register is known as Base Address Register 0 for standard PCI devices.
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