参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 19/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
f For information about BER, refer to “BER Estimator” on page 3–10 .
4. For parallel architectures, you can select one of the following optimizations:
2–5
■
■
■
None . The core uses combined continuous and block decoding. With this
option only, you can turn on the Best State Finder option.
Block . This option implements a single traceback engine with memory to hold
the whole size of the block.
Continuous . This option implements a fixed traceback length, which reduces
the size of the architecture.
5. Click the Code Sets tab ( Figure 2–5 ).
Figure 2–5. Code Set Configuration
6. Enter the code set information that you require:
a. Choose the Number of Code Sets . Choose a value greater than one, for
multiple code sets.
b. Select Decimal or Octal .
c. Choose either Viterbi mode, V , or trellis coded modulation (TCM) mode, T .
d. Enter values for the required polynomials GA , GB , GC , GD , GE , GF , and GG.
e. Enter a value for the number of coded bits, N .
f. Enter the constraint length, L , for the code set.
f For information about multiple code sets, refer to “Code Sets Tab” on
page 3–12 .
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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