参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 41/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
Signals
Figure 3–11 shows the Viterbi decoder Avalon-ST interfaces.
Figure 3–11. Avalon-ST Interface
3–15
ena
v al
Master (Sink)
sink_ena_master
sink_ v al
Sla v e (Source)
source_ena_sla v e
source_ v al
ena
v al
User Module
V iter b i Decoder
User Module
Sla v e (Source)
sop
eop
dat
sink_sop
sink_eop
rr/eras_sym
source_sop
source_eop
dec b it
sop
eop
dat
Master (Sink)
Avalon-ST Interface
Table 3–7 shows the global signals.
Table 3–7. Global Signals
Avalon-ST Interface
Signal Name
clk
reset
Description
The main system clock. The whole MegaCore function operates on the rising edge of clk .
Reset. The entire decoder is asynchronously reset when reset is asserted high. The reset signal resets
the entire system. The reset signal must be deasserted synchronously with respect to the rising edge
of clk .
Table 3–8 shows the Avalon-ST sink signals.
Table 3–8. Avalon-ST Sink Signals (Part 1 of 2)
Signal Name
Avalon-ST
Name
Direction
Description
Data transfer enable signal. sink_rdy is driven by the interface sink
and controls the flow of data across the interface. sink_rdy behaves
as a read enable from sink to source. When the source observes
sink_rdy asserted on the clk rising edge, it can drive the Avalon-ST
sink_rdy
ready
Output
data interface signals and assert sink_val as early as the next clock
cycle, if data is available. In the hybrid architecture, sink_rdy is
asserted for one clock cycle at a time. If data is not available at the time,
you have to wait for the next sink_rdy pulse. Previously called
sink_ena_master .
Data valid signal. sink_val indicates the validity of the data signals.
sink_val is updated on every clock edge where sink_rdy is sampled
asserted, and holds its current value along with the dat bus where
sink_rdy is sampled deasserted. When sink_val is asserted, the
sink_val
val
Input
Avalon-ST data interface signals are valid. When sink_val is
deasserted, the Avalon-ST data interface signals are invalid and must be
disregarded. To determine whether new data has been received, the sink
qualifies the sink_val signal with the previous state of the sink_rdy
signal.
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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