参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 25/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
2–11
MegaWizard Plug-In Manager Flow
Table 2–1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the IP Toolbench report vary
based on whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files
Filename
< variation name > .bsf
< variation name >.cmp
< variation name >.html
< variation name >.qip
< variation name > .vho or .vo
< variation name >. vhd , or .v
(1)
Description
Quartus II symbol file for the MegaCore function variation. You can use this file in
the Quartus II block diagram editor.
A VHDL component declaration file for the MegaCore function variation. Add the
contents of this file to any VHDL architecture that instantiates the MegaCore
function.
A MegaCore function report file in hypertext markup language format.
A single Quartus II IP file is generated that contains all of the assignments and other
information required to process your MegaCore function variation in the Quartus II
compiler. You are prompted to add this file to the current Quartus II project when
you exit from the MegaWizard.
VHDL or Verilog HDL IP functional simulation model.
A MegaCore function variation file, which defines a VHDL or Verilog HDL top-level
description of the custom MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling your design in the
Quartus II software.
< variation name > _nativelink.tcl
< variation name > _syn.vhd or _syn.v
(2)
< variation name > _testbench.vhd
< variation name > _vsim_script.tcl
a_rcvsym.txt
a_txsym.txt
BER_report.txt
block_period_stim.txt
tcm_rcv_sector.txt
transbit.txt
Tcl Script that sets up NativeLink in the Quartus II software to natively simulate the
design using selected EDA tools.
An optional timing and resource netlist for use in some third-party synthesis tools.
The testbench.
Starts the MegaCore function simulation in the ModelSim simulator.
Contains the received bits that are corrupted with a signal-to-noise ratio you specify
in IP Toolbench.
Contains the encoded bits.
Contains the number of errors, the BERs and their location for the test data.
The testbench stimuli, which change for every block.
Contains the sector numbers for TCM codes for decoding the testbench. The file is
empty if there are no TCM codes defined.
Contains the bits that generate the test data.
Notes to Table 2–1 :
(1) The < variation name > prefix is automatically added by IP Toolbench.
(2) The _syn.vhd or _ syn.v file is only generated when it is enabled in the Set Up Simulation page of the IP Toolbench interface.
2. After you review the generation report, click Exit to close IP Toolbench. Then click
Yes on the Quartus II IP Files prompt to add the . qip file describing your custom
MegaCore function to the current Quartus II project.
f Refer to the Quartus II Help for more information about the MegaWizard Plug-In
Manager.
You can now integrate your custom variation into your system design, simulate, and
compile the design.
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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