参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 34/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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3–8
Chapter 3: Functional Description
Trellis Termination
The decoder uses the coded bits (c 1 , c 0 ) to select the branch metric number, which is
used to decide where to connect the branch metrics to the rr input of the Viterbi
decoder. Branch metric 3 goes to the most significant bits (MSB) of rr ; branch metric 0
goes to the least significant bits (LSB) of rr .
Trellis Termination
Block decoding requires the implementation of a technique to properly decode the
last bits of the block. The technique adapts to whatever is happening in the
convolutional encoder. Two techniques are described.
With the first technique, the convolutional encoder is fed with a block and then
terminated with ( L – 1) bits taken from the end of the block. These bits are unknown.
The initial state of the convolutional encoder is set with the last ( L – 1) information
bits.
This technique, known as “tail-bitting”, is decoded by replicating the block at the
decoder or double feeding the block into the decoder. By decoding in the middle
point, the trellis is forced into the state that is both the initial state and the end state.
From the first decoding block, you can take the last half of the block; from the second
decoded block (or second pass through the decoder), you can obtain the first half of
the bits of the block.
1
In tail-bitting technique, the block size must be large enough to train the decoder,
otherwise there is BER loss.
With the second technique, the convolutional encoder is initialized to zero. So the
initial state of the trellis is known to be zero. The last ( L – 1) bits to the convolutional
encoder are known. They serve the purpose of bringing the convolutional encoder to
a known end state. The decoder then uses this information to set the end state of the
trellis with tr_init_state .
The tr_init_state signal is derived from the last ( L – 1) bits of the block in reverse
order.
For example, for a block that ends in:
...000101
If L = 5 and the last ( L – 1) = 4 bits are known, tr_init_state is set as 0101 , which
reversed and in binary is 1010 , or 10 in decimal.
IP Toolbench generates tr_init_state as if the last ( L – 1) bits of each block are
known.
Trellis Initiation
The parallel decoder always starts its trellis from state zero for a new block. The
hybrid however allows you to set the initial state (usually zero) with bm_init_state .
This signal has range from 0 to 2 (L – 1) – 1 , which are the trellis states.
The bm_init_value signal initiates the state metric of the state indicated by
bm_init_state . All other states are initialized with zero. The appropriate value for
this port is approximately 2 (bmgwide – 2) or any value between 2 (N + softbits) to 2 (bmgwide – 1) .
Viterbi Compiler
User Guide
November 2013 Altera Corporation
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