参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 36/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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3–10
Chapter 3: Functional Description
Parameters
Architecture Tab
Table 3–3 shows the options that can be set in the Architecture tab
Table 3–3. Architecture Tab Options
Parameter
Hybrid or Parallel
BER
Node Sync
Optimizations
Value
–
On or Off
On or Off
None,
Continuous,
or Block
Description
Selects the hybrid or parallel architecture.
Specifies the BER estimator option, refer to “BER Estimator” on page 3–10 .
Specifies the node synchronization option (only available when BER option is on).
Specifies the optimization for the parallel decoder. if you select None you can turn on
Best State Finder . However, to use less logic, turn off Best State Finder .
BER Estimator
Figure 3–7 shows a block diagram of the BER estimator.
Figure 3–7. BER Estimator
Input Symbols
Viterbi
Decoder
Convolutional
Encoder
Compare
BER Output
and Count
(numerr)
Delay
The BER estimator option uses a re-encode and compare approach for estimating the
number of errors in the input data. In cases where the signal-to-noise ratio is
sufficiently high to allow the decoder to decode an error-free output, the BER
estimation is very close to the actual channel BER.
When the decoder is not decoding an error-free output, the estimated BER is higher
and more random than the actual channel BER, which introduces a degree of
uncertainty directly proportional to the output errors ( Figure 3–8 on page 3–11 ).
Viterbi Compiler
User Guide
November 2013 Altera Corporation
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