参数资料
型号: IP-VITERBI/SS
厂商: Altera
文件页数: 42/50页
文件大小: 0K
描述: IP VITERBI LOW-SPEED
标准包装: 1
系列: *
类型: MegaCore
功能: Viterbi 低速编译器
许可证: 初始许可证
3–16
Chapter 3: Functional Description
Signals
Table 3–8. Avalon-ST Sink Signals (Part 2 of 2)
Signal Name
Avalon-ST
Name
Direction
Description
Start of packet (block) signal. sop delineates the packet boundaries on
sink_sop
sop
Input
the rr bus. When sink_ sop is high, the start of the packet is present on
the rr bus. sink_ sop is asserted on the first transfer of every packet
This signal applies to block decoding only.
End of packet (block) signal. sink_ eop delineates the packet boundaries
sink_eop
eop
Input
on the rr bus. When sink_ eop is high, the end of the packet is present
on the dat bus. sink_ eop is asserted on the last transfer of every
packet. This signal applies to block decoding only.
Data input, which takes in n symbols, each softbits wide per clock.
rr
(1)
dat
(2)
Input
“Encoding Scheme” on page 3–2 describes the correspondence of the
input symbols with the output of a convolutional encoder. For the
mappings of the individual soft symbols, refer to Table 3–1 .
eras_sym[Nmax:1]
dat
(2)
Input
When asserted, eras_sym Indicates an erased symbol.
Notes to Table 3–8 :
(1) In TCM mode the rr width is (2 N × softbits :1); in Viterbi mode the rr width is ( nmax × softbits :1).
(2) Both rr and eras_sym are seen as Avalon-ST dat inputs.
Table 3–9 shows the Avalon-ST source signals.
Table 3–9. Source Signals
Signal
Avalon-ST
Name
Direction
Description
Data transfer enable signal. source_rdy is driven by the sink interface and
used to control the flow of data across the interface. ena behaves as a read
enable from sink to source. When the source observes source_rdy
asserted on the clk rising edge it drives, on the following clk rising edge,
source_rdy
ready
Input
the Avalon-ST data interface signals and asserts source_val . The sink
captures the data interface signals on the following clk rising edge. If the
source is unable to provide new data, it deasserts source_val for one or
more clock cycles until it is prepared to drive valid data interface signals.
Previously called source_ena_slave .
source_val
source_sop
source_eop
decbit
val
sop
eop
dat
Output
Output
Output
Output
Data valid signal. source_val is asserted high for one clock cycle,
whenever there is a valid output on the decbit signal.
Start of packet (block) signal. if you select continuous optimization, this
signal is left open and you must remove it from the testbench.
End of packet (block) signal. if you select continuous optimization, this
signal is left open and you must remove it from the testbench.
The decbit signal contains output bits when source_val is asserted.
Table 3–10 shows the configuration signals.
Table 3–10. Configuration Signals (Part 1 of 2)
Signal Name
ber_clear
state_node_sync[log2(Nmax):1]
Viterbi Compiler
User Guide
Description
Reset for the BER counter. Only for the BER block option.
Specifies the node synchronization rotation to rr .
The state_node_sync signal is latched when sink_sop is asserted.
November 2013 Altera Corporation
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