参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 44/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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3–18
Chapter 3: Functional Description
Signals
Table 3–11. Status Signals (Part 2 of 2)
Signal
bestadd[(L-1):1]
Description
The best address state. The address corresponding to the best metric as it is being
found by the best state finder. The metric of this state if shown in bestmet . This signal
is left open, if you select continuous optimization, or if you select none for optimization
and turn off best state finder in IP Toolbench.
Note to Table 3–11 :
(1) Used only when you select the BER estimator option.
Timing Diagrams
Figure 3–12 shows the hybrid Viterbi decoder input timing diagram. The sink_rdy
signal is asserted for one clock cycle in every Z clock cycles. (For the values of Z , refer
to “Latency Calculator” on page 3–14 .) If the decoder becomes full because data is not
being collected on the source side, it may deassert sink_rdy until it can accept new
data. The decoder only accepts data, if sink_rdy is asserted.
Figure 3–12. Input Timing Diagram—Hybrid
clk
sink_rdy
sink_ v al
sink_sop
sink_eop
rr[8:1]
77
88
88
Figure 3–13 shows the parallel Viterbi decoder input timing diagram.
Figure 3–13. Input Timing Diagram—Parallel
clk
sink_rdy
sink_ v al
sink_sop
sink_eop
rr[8:1]
v alid data
Figure 3–14 and 3–19 show output timing diagrams. Figure 3–14 shows the
source_val signal asserted initially for 8 or 16 clock cycles. It is then asserted for the
number of clock cycles corresponding to the amount of remaining data, if source_rdy
remains asserted.
Viterbi Compiler
User Guide
November 2013 Altera Corporation
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