参数资料
型号: IP-VITERBI/SS
厂商: Altera
文件页数: 7/50页
文件大小: 0K
描述: IP VITERBI LOW-SPEED
标准包装: 1
系列: *
类型: MegaCore
功能: Viterbi 低速编译器
许可证: 初始许可证
Chapter 1: About This Compiler
Device Family Support
Table 1–1. Viterbi Compiler Release Information (Part 2 of 2)
1–3
Product IDs
Vendor ID
Item
Description
0037 (parallel architecture)
0038 (hybrid architecture)
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata .
Altera verifies that the current version of the Quartus ? II software compiles the
previous version of each MegaCore ? function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release."
Device Family Support
Altera offers the following device support levels for Altera IP cores:
Preliminary support —Altera verifies the IP core with preliminary timing models
for this device family. The IP core meets all functional requirements, but might still
be undergoing timing analysis for the device family. You can use it in production
designs with caution.
Final support —Altera verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family and can be used in production designs.
Table 1–2 shows the level of support offered by the Viterbi MegaCore functions to
each of the Altera device families.
Table 1–2. Device Family Support
Arria ? II GX
Arria II GZ
Arria V
Device Family
Final
Final
Full
Support
Cyclone ?
III
Final
Cyclone III LS
Cyclone IV GX
Stratix ? III
Stratix IV GT
Stratix IV GX/E
Stratix V
Other device families
Final
Final
Final
Final
Final
Full
No support
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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