参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 37/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
Parameters
3–11
1
For a TCM code, the BER block does not produce a meaningful output ( numerr )
because the BER block does not compute errors at the input for TCM codes.
Figure 3–8. Graph comparing Actual BER with Estimated BER
1.00e-01
BER 1.00e-02
Actual BER
Estimated BER
1.00e-03
3.00
3.50
4.00
4.50
5.00
5.50
6.00
Signal-to-Noise Ratio
Node Synchronization
If you are not using external synchronization, you may not know the order of your N
bits. The node synchronization option allows you to rotate the rr inputs until the
decoder is in synchronization. To use node synchronization, you observe the BER and
keep changing state_node_sync to rotate the rr inputs until you get the correct value
for the BER.
Figure 3–9 shows the node synchronization block diagram.
Figure 3–9. Node Synchronization
state_node_sync
rr(1)
rr(2)
...
rr(N)
Barrel
Rotator
RR(1)
RR(2)
...
RR(N)
Note:
(1) The barrel rotator is only implemented if you select the node synchronization option.
The following equation represents node synchronization:
RR [i] = rr [(( state_node_sync + i – 1) mod N ) + 1]
where i is 1 to N.
RR and rr are treated as an array of width N of busses softbits wide. The range of
valid values for state_node_sync is 0 to ( N – 1).
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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