参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 45/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
3–19
MegaCore Verification
Figure 3–14 shows the typical ending of a block or packet in the Avalon-ST interface
on the source (Viterbi) to the sink (user) side connection.
Figure 3–14. Output Timing Diagram—Example 1
clk
source_sop
source_eop
source_rdy
source_ v al
dec b it
Figure 3–15 on page 3–19 shows a different ending.
Figure 3–15. Output Timing Diagram—Example 2
clk
source_sop
source_eop
source_rdy
source_ v al
dec b it
Figure 3–16 shows a depuncturing timing diagram and shows eras_sym for the
pattern 110110 (puncturing rate 3/4). By changing the eras_sym pattern you can
implement virtually any depuncturing pattern you require.
Figure 3–16. Depuncturing Timing Diagram
clk
ena
v al
sop
rr[8:5]
rr[4:1]
B
8
X
7
7
X
A
D
X
9
7
X
eras_sym[2]
eras_sym[1]
MegaCore Verification
The MegaCore verification includes an automated regression test suite, which is
described in the following paragraphs.
Scripts drive the simulation at RTL level. Data is randomly generated and encoded.
The original transmitted bits are stored in a file transbit.txt . Optionally, Gaussian
noise is added as a channel model and the data is formatted for use by the decoder ’s
testbench. The file that feeds the testbench is a_rcvsym.txt . The testbench collects the
decoder ’s decoded bits and stores them in decoded.txt . Those bits are compared with
the original in transbit.txt .
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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