参数资料
| 型号： | IP-VITERBI/SS |
| 厂商： | Altera |
| 文件页数： | 31/50页 |
| 文件大小： | 0K |
| 描述： | IP VITERBI LOW-SPEED |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | Viterbi 低速编译器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
3–5
Trellis Coded Modulation
The four-state trellis is the trellis for the 1/2 rate convolution encoder with the
addition of parallel paths in each transition to accommodate the uncoded bit c 2 . Thus,
the decoder uses the coded bits (c 1 , c 0 ) to select one of the four subsets that contain
two signal points each, and uses the uncoded bit to select one of the two signal points
within each subset.
Figure 3–4. Four-State Trellis
000 = (c 2 c 1 c 0 )
00
111
100
011
10
011
111
000
100
001
01
110
010
101
010
110
11
001
101
Figure 3–5 shows one implementation of the Viterbi decoder as a Trellis decoder. The
decoder processes a symbol upon arrival to obtain four branch metric values and a
sector number. The branch metrics enter the Viterbi decoder in trellis mode and the bit
that is encoded is obtained. This bit stream is then re-encoded and the output of this
encoder is used in conjunction with the sector number information to retrieve the
uncoded bit. All the logic is implemented in the provided testbench.
The branch metric values and sector number values are generated by IP Toolbench, so
there is no logic to create those values. The testbench reads the sector number when it
is needed, hence there is no delay functionality for that, nor is there rotation. The data
created by IP Toolbench has no phase error introduced so the phase is aligned.
However, in a real system, you must calculate the phase.
November 2013
Altera Corporation
Viterbi Compiler
User Guide
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