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参数资料
| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 18/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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2–8
c
Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Turning off the Display entity name for node name setting prevents the
timing analysis script from completing successfully. To enable this setting,
open the Assignments menu and click Settings . On the Settings page, click
Compilation Process Settings, and then click More Settings . In the Name
list, select Display entity name for node name and in the Setting list, select
On .
The results show how much slack you have for each of the various timing
requirements—negative slack means that you are not meeting timing. The Message
window shows various timing margins for your design.
If the verify timing script reports that your design meets timing, you have
successfully generated and implemented your DDR or DDR2 SDRAM Controller.
If the timing does not reach your requirements, adjust the resynchronization and
postamble clock phases on the IP Toolbench Manual Timings tab (refer to “Manual
f
1
f
To view the constraints in the Quartus II Assignment Editor, choose Assignment
Editor (Assignments menu).
If you have “?” characters in the Quartus II Assignment Editor, the Quartus II
software cannot find the entity to which it is applying the constraints, probably
because of a hierarchy mismatch. Either edit the constraints script, or enter the correct
hierarchy path in the Hierarchy tab (refer to step 24 on page 2–13 ).
Program a Device
After you have compiled the SOPC Builder design, you can perform gate-level
simulation (refer to “Simulate the SOPC Builder Design” on page 2–6 ) or program
your targeted Altera device to verify the SOPC Builder design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or
DDR2 SDRAM controller MegaCore function before you purchase a license.
OpenCore Plus evaluation allows you to produce a time-limited programming file.
f
For more information on OpenCore Plus hardware evaluation using the DDR or
MegaWizard Plug-In Manager Design Flow
MegaWizard Plug-In Manager design flow involves the following steps:
1. Create a custom variation of the DDR or DDR2 SDRAM controller MegaCore
function using IP Toolbench from the MegaWizard Plug-In Manager.
? March 2009 Altera Corporation
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| IPR-RSENC | IP REED-SOLOMON ENCODER RENEW |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SLITE2 | 功能描述:开发软件 SerialLite II MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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