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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 96/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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B–2
3. The DDR SDRAM device on the Nios Development Board, Cyclone II Edition, has
a minimum operating frequency of 77 MHz. So your design must have an f MAX
greater than or equal to 77 MHz to use the DDR SDRAM. If a Quartus II
compilation of your system results in an f MAX less than 77 MHz, turn on some of the
following Quartus II optimizations to increase the f MAX :
a. Change the optimization technique to speed:
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Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings .
In Optimization Technique , select Speed .
b. Turn on one-hot state machine processing:
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Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings .
For State Machine Processing , choose One-Hot .
c. Turn off multiplexer restructuring:
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Choose Settings (Assignments menu).
Choose Analysis & Synthesis Settings .
For Restructure Multiplexers , choose Off .
d. Turn on physical synthesis in the fitter:
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Choose Settings (Assignments menu).
Expand Fitter Settings by clicking the + symbol.
Choose Physical Synthesis Optimizations .
Turn on Perform physical synthesis for combinational logic .
Turn on Perform register duplication .
Turn on Perform register retiming .
For Physical synthesis effort , select Normal .
4. When you have made these settings, save the project and recompile the design in
the Quartus II software.
1
f
These settings significantly increase the time required to compile the design in the
Quartus II software, but are likely to increase the f MAX .
5. On the Nios Development Board Cyclone II Edition (rev00 only), the DDR
SDRAM pins ras and cas are accidentally switched on the PCB schematic. So to
maintain consistency between the PCB schematic and Quartus II pin assignments,
these two pins must also be switched in your Quartus II top-level design when
targeting the Nios Development Board, Cyclone II Edition (rev00 only).
For the correct connection of the ras and cas pins, refer to the Cyclone II 2C35
standard example design shipped with the Nios II Development Kit.
? March 2009 Altera Corporation
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