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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 99/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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C. HardCopy II Design Walkthrough
This walkthrough explains the additional steps that are needed to use the DDR or
DDR2 SDRAM Controller MegaCore function in a HardCopy II design.
f
You can create a HardCopy II design either with the main target set to a HardCopy II
device and a Stratix II migration device, or with the main revision targeting a Stratix II
device and a companion revision targeting HardCopy II device.
To create a HardCopy II design, follow these steps:
1. Create a new Quartus II project and choose a family, a device, and a companion
device.
1
Altera recommends you choose a –4 speed grade device.
2. Launch IP Toolbench from the MegaWizard Plug-In Manager
3. Parameterize your custom variation.
4. Choose the constraints.
1
HardCopy II devices do not have dedicated hardware for DDR or DDR2
SDRAM capture on as many pins as the Stratix II companion, so there are
less DQS groups available.
5. Generate the variation.
6. Compile the design, which adds placement constraints for critical registers in the
read part of the datapath, and produces a report of the predicted timing margins.
7. The timing report that appears automatically is not available to the HardCopy
Design Centre, therefore add a set of timing constraints to help timing closure, by
running the DDR and DDR2 SDRAM timing wizard (DTW)—choose Tcl scripts
(Tools menu) and choose dtw .
f
8. To save time re-entering the parameters of the DDR or DDR2 SDRAM Controller
MegaCore function, import the parameters from the < variation
name > _ddr_setting.txt file, by clicking Import… on the third page of the wizard.
9. The DTW also needs an estimate of the t CO on the pins that drive the clock to the
DDR or DDR2 SDRAM. When the design has been compiled extract these
automatically in the relevant pane of the wizard.
10. Click Finish . The DTW adds timing constraints to the project, which are preserved
when migrating to HardCopy II devices.
? March 2009
Altera Corporation
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相关代理商/技术参数 |
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| IP-RSENC | 功能描述:开发软件 Reed-Solomon Encoder MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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