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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 42/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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3–6
Chapter 3: Functional Description
Device-Level Description
Figure 3–3. Datapath Timing
[1]
[2]
[3]
[4]
clk
Write Interface
control_doing_wr
control_wdata_valid
control_dqs_burst
control_wdata
A269
32A0 4671 31F5
control_be
1
0
3
0
Read Interface
control_doing_rd
control_rdata
DDR SDRAM
Interface
AD75 D739
D31D3A50
DDR Command NOP ACT NOP
RD
NOP PCH NOP ACT NOP
WR
NOP
ddr_dm
ddr_dq
ddr_dqs
1. The controller asserts control_doing_rd to enable the DQ input registers so
that the read data is captured (the datapath delays this signal to match the CAS
latency). In this case, it is expecting four cycles of read data, so it holds the signal
asserted for four clock cycles. At the end of the burst, the signal is deasserted to
disable the DQ capture registers, which avoids them being clocked unnecessarily
after the DQS read postamble.
2. The controller state machine asserts the control_wdata_valid signal as soon
as it knows that it is doing a write. The signal does not need to be asserted this
early. However, in this example it simplifies the controller design. The write data
is only valid in that clock cycle and is held in the wdata registers until the write
happens.
3. The controller asserts control_doing_wr for the length of the burst (four beats)
to indicate that it is doing a write. This signal controls the output enables of the
DQ signals.
4. The controller reasserts control_wdata_valid to request the next write data
once it knows it is now writing to the memory
1
If you use DDR2 SDRAM and design your own controller, you need to take
the variable write latency into account when generating the
control_doing_wr signal.
? March 2009 Altera Corporation
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