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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 43/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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Chapter 3: Functional Description
3–7
Device-Level Description
Designing Your Own Controller
The state machine that issues the read commands generates control_doing_rd
and it starts when the read command is issued to the memory and stays asserted for
the length of the burst. It is delayed inside the controller to cope with the following
options:
■
■
■
Insert pipeline registers on address and command outputs
Registered DIMM
Insert extra pipeline registers in the datapath
The datapath is generated with a pipeline to cope with CAS latency in each DQS
group rather than inside the controller. Duplicating this pipeline across the
bytegroups makes timing easier to meet on the critical postamble logic—the last
register in this pipeline feeds the postamble control register. If you design you own
controller, you need to generate the datapath for the right CAS latency, otherwise this
pipeline is the wrong length.
The enabling and disabling of the capture registers (controlled by the
control_doing_rd signal) is disabled in RTL simulation because it relies so heavily
on timing in the system to work. So in RTL simulation, the capture registers are
always enabled and varying the timing of the control_doing_rd signal does not
change the behavior of the datapath.You should use gate-level simulations to test the
exact timings of this signal if you design your own controller.
The same source that generates control_doing_rd generates the
local_rdata_valid signal and it is delayed inside the controller by the same
amount. In addition, it is delayed to take the following datapath options into account:
■
■
Reclock resynchronized data to the positive edge
Insert intermediate resynchronization registers
The local_rdata_valid signal is also delayed by 4 + R cycles, where R is the
resynchronization cycle as predicted by the wizard. For example, if the
resynchronization cycle is 2, Reclock resynchronized data to the positive edge is
turned on, and Insert intermediate resynchronization registers is turned off, the
local_rdata_valid signal should be seven cycles later than the
control_doing_rd signal (4 + 2 + 1 + 0 = 7).
The control_doing_wr signal controls the output enables on the DQ and DQS
pins. The state machine that issues the write commands generates it and it is delayed
inside the controller to cope with the following options:
■
■
■
Insert pipeline registers on address and command outputs
Registered DIMM
Insert extra pipeline registers in the datapath
For DDR SDRAM, the write latency is fixed at 1 clock cycle. You should issue the
control_doing_wr signal so that it starts when you issue the write command to the
memory and ensure it stays asserted for the length of the burst.
For DDR2 SDRAM, the write latency varies with the CAS latency, which the
controller takes into account and it delays the control_doing_wr signal to match.
You should issue the control_doing_wr signal (CAS latency – 2) clock cycles after
the write command and ensure it stays asserted for the length of the burst.
? March 2009
Altera Corporation
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