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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 32/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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2–22
Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
2. Launch your simulation tool inside this directory and create the following
libraries:
■
■
< device name > _ver
auk_ddr_user_lib
3. Compile the files in Table 2–5 into the appropriate library.
Table 2–5. Files to Compile—Verilog HDL Gate-Level Simulations
Library
< device name > _ver
auk_ddr_user_lib
Filename
< QUARTUS ROOTDIR > /eda/sim_lib/ < device name > _atoms.v
< project directory > /testbench/simulation/ < simulator name > /<toplevel_name>.vo (1)
< project directory > /testbench/ < testbench name > .v
(1) If you are simulating the slow or fast model., the .vho file has a suffix _min or _max added to it. Compile whichever file is appropriate. The
Quartus II software creates models for the simulator you have defined in a directory simulation/ < simulator name > in your < project name >
directory..
4. Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not to use the
insert extra delays in the system, because these are applied inside the gate level
model. Configure your simulator to use transport delays, a timestep of
picoseconds, and to include the < device name > _ver library.
Compile the Example Design
You can now edit the PLL(s) and use the Quartus II software to compile the example
design and perform post-compilation timing analysis.
Edit the PLL
The IP Toolbench-generated example design includes a PLL, which has an input to
output clock ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In
addition, IP Toolbench correctly sets all the phase offsets of all the relevant clock
outputs for your design. You can edit the PLL input clock to make it conform to your
system requirements. If you re-run IP Toolbench, it does not overwrite this PLL, if
you turn off Automatically generate the PLL , so your edits are not lost.
1
1
f
If you turn on Use fed-back clock , IP Toolbench generates a second PLL—the fed-back
PLL. You need not edit the fed-back PLL.
If you change the clock input frequency on the PLL, you must change the
REF_CLOCK_TICK_IN_PS parameter in the < project name > _tb.v or .vhd file.
To edit the example PLL, follow these steps:
1. Choose MegaWizard Plug-In Manager (Tools menu).
2. Select Edit an existing custom megafunction variation and click Next .
3. In your Quartus II project directory, for VHDL choose ddr_pll_ <device name> .vhd ;
for Verilog HDL choose ddr_pll_ <device name> .v .
? March 2009 Altera Corporation
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