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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 89/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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A–11
DQS Postamble
The DDR and DDR2 SDRAM Controller Compiler provides this DQS postamble logic.
IP Toolbench automatically chooses the best postamble logic clocking scheme for your
system based on the parameters that you enter. The postamble clock can be the
positive or negative edge of either the system clock or the write clock. If a safe
postamble cannot be guaranteed using one of these four phases, a separate output of
the PLL is used as the postamble clock. If the postamble clock phase is close (<90 ° ) to
the positive edge of the system clock, an alternative postamble control
synchronization scheme is used.
Postamble Logic
devices, the dq_enable register clocked by the DQS signal is placed in an LE close to
the associated DQ group to drive their input clock enables. The data input to the
dq_enable register is set to GND, and the preset is connected to logic generated by
the controller. The postamble logic ensures that the register is released from preset
prior to the last active negative edge of DQS, so that the dq_enable signal goes low
with the last active negative edge of DQS. The input clock enable is therefore disabled
before DQS transitions to high-impedance at the end of the DQS read postamble.
You can specify your own postamble clock instead of using the automatically selected
one, on the Manual Timing tab of the wizard. Also, you can disable the DQS
postamble logic completely, on the Manual Timing tab of the wizard.
DQS postamble logic is not required for DDR and DDR2 SDRAM if you are using a
dedicated read data capture clock (non-DQS mode). As such, in non-DQS mode the
wizard disables the DQS postamble logic.
Table A–6. Manual Postamble Parameters
Cycle
0, 1, 2, 3, 4, 5, 6
clk
write_clk
clk
write_clk
Clock
Rising
Falling
Falling
Rising (2)
Edge
Phase ( ° )
0 (1)
90
180
270
(1) Postamble cycle 0 phase 0 is defined as the first rising edge of clk capable of generating the postamble enable
preset signal for CAS latency = 2.
(2) Use the intermediate postamble option to guarantee timing
? March 2009
Altera Corporation
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