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| 型号： | IPR-SDRAM/DDR |
| 厂商： | Altera |
| 文件页数： | 68/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR SDRAM CONTROLLER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR SDRAM 控制器 |
| 许可证： | 续用许可证 |
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3–32
Chapter 3: Functional Description
Parameters
Memory
Table 3–11. Memory Interface Parameters
Parameter
Data bus width
Value
≥ 8
Units
Bits
Description
The width of your DDR or DDR2 SDRAM data interface. Your local
interface is twice the width of the memory interface. This value
depends on:
■
■
■
The memory
Bandwidth requirement
Number of DDIO pins available on the selected FPGA device
Number of chip selects
1, 2, 4, or 8
—
The number of chip selects in your memory interface. This is
equivalent to the depth of your memory in terms of number of
chips. This value depends on the type of memory DIMM selected.
If there are two DIMMs and the memory modules on both DIMMs
have two ranks, the number of chip selects is 4.
Number of chip selects
per DIMM
1 or 2
—
The number of chip selects on each DIMM in your memory
system. This option is completely dependent on the type of
external SDRAM that you are using. SDRAMs may come in two
memory chips (called rank) connected in parallel, with only a
unique chip enable signal. This configuration allows the two ranks
to share address and data lines. Selectively asserting only one
chip enable signal at a time, allows twice the memory depth
compared with only a single chip.
If there are two memory chips in the memory module, select 2,
otherwise select 1.
Use dedicated PLL
outputs
On or off
—
Turn on to use dedicated PLL outputs to generate the clocks,
which is recommended for HardCopy II devices.
HardCopy II designs use dedicated PLL outputs for noise
immunity, better signal integrity, and minimal variation over
process, temperature, and voltage.
When turned off, the ALTDDIO megafunction generates the clock
outputs.
Number of clock pairs
from FPGA to memory
1 to 6
—
The number of differential clock pairs driven from the FPGA to the
memory. More clock pairs reduce the loading of each output.
Table 3–12. Memory Property Parameters (Part 1 of 2)
Parameter
Row address bits
Column address bits
Bank address bits
Precharge address bit
Range
10 to 14
8 to 13
2 or 3
8 or 10
Units
Bits
Bits
Bits
–
Description
The number of row address bits for your memory.
The number of column address bits for your memory.
The number of bank address bits for your memory.
The address bit to use as the precharge pin.
? March 2009 Altera Corporation
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