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参数资料
| 型号： | K4T56163QI-ZLD50 |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84 |
| 封装： | ROHS COMPLIANT, FBGA-84 |
| 文件页数： | 9/42页 |
| 文件大小： | 727K |
| 代理商： | K4T56163QI-ZLD50 |
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Rev. 1.0 October 2007
DDR2 SDRAM
K4T56163QI
17 of 42
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
min
max
min
max
DQ output access time from CK/CK
tAC
- 400
400
-450
+450
-500
+500
-600
+600
ps
DQS output access time from CK/CK
tDQSCK
- 350
350
-400
+400
-450
+450
-500
+500
ps
CK high-level width
tCH
0.450.550.450.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.450.550.450.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,t
CH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x
ps
20,21
Clock cycle time, CL=x
tCK
2500
8000
3000
8000
3750
8000
5000
8000
ps
24
DQ and DM input hold time
tDH(base)
125
x
175
x
225
x275
x
ps
15,16,
17,20
DQ and DM input setup time
tDS(base)
50
x
100
x
100
x150
x
ps
15,16,
17,21
Control & Address input pulse width for each input tIPW
0.6
x
0.6
x
0.6
x0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x
0.35
x
0.35
x0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
x
tAC max
x
tAC max
x
tAC max
x
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
tAC min
tAC max
tAC min
tAC max
ps
27
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tAC
min
tAC max
2*tAC
min
tAC max 2* tACmin tAC max 2* tACmin
tAC max
ps
27
DQS-DQ skew for DQS and associated DQ sig-
nals
tDQSQ
x
200
x
240
x
300
x
350
ps
22
DQ hold skew factor
tQHS
x
300
x
340
x
400
x
450
ps
21
DQ/DQS output hold time from DQS
tQH
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
19
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH(base)
250
x
275
x
375
x
475
x
ps
14,16,
18,23
Address and control input setup time
tIS(base)
175
x
200
x
250
x
350
x
ps
14,16,
18,22
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
28
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
28
Active to active command period for 1KB page
size products
tRRD
7.5
x
7.5
x7.5
x
7.5
x
ns
12
13.3 Timing Parameters by Speed Grade
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