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Figure 7.4-2
PWM Mode Timing Chart (Retrigger enabled) ........................................................................ 234
Figure 7.5-1
One-shot Mode Timing Chart (Retrigger Disabled) ................................................................. 235
Figure 7.5-2
One-shot Mode Timing Chart (Retrigger Enabled) .................................................................. 236
Figure 7.6-1
PPG Timer Interrupt Resources and Timing Chart .................................................................. 237
Figure 7.6-2
PPG Timer Interrupt Timing Chart for an Interrupt by Borrow ................................................. 237
Figure 7.6-3
PPG Timer Interrupt Timing Chart for a Interrupt by Compare Match ..................................... 237
Figure 8.1-1
Block Diagram of the External Interrupt/NMI Control Section ................................................. 240
Figure 8.1-2
Registers of the External Interrupt/NMI Control Section .......................................................... 240
Figure 8.3-1
External Interrupt Processing .................................................................................................. 243
Figure 8.4-1
Clearance of the Resource Hold Circuit at Level Setting ........................................................ 244
Figure 8.4-2
Interrupt Resource and Interrupt Request to the Interrupt Controller when Interrupt is
Enabled .................................................................................................................................. 244
Figure 8.5-1
NMI Request Detection Section .............................................................................................. 245
Figure 9.1-1
Block Diagram of the Delayed Interrupt Module ...................................................................... 248
Figure 9.1-2
Registers of the Delayed Interrupt Module .............................................................................. 248
Figure 10.2-1
Block Diagram of the Interrupt Controller ................................................................................ 253
Figure 10.3-1
Figure 10.3.1 Registers of the Interrupt Controller ................................................................. 254
Figure 10.7-1
Hardware Configuration for Using the Hold Request Cancel Request .................................... 263
Figure 10.7-2
Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a) ................................... 264
Figure 10.7-3
Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a > b) ............................. 264
Figure 11.2-1
Block Diagram of the A/D Converter ....................................................................................... 269
Figure 11.3-1
Registers of the A/D Converter ................................................................................................ 270
Figure 11.5-1
Data Protection Function Flow ................................................................................................ 280
Figure 12.2-1
UART Block Diagram .............................................................................................................. 285
Figure 12.3-1
UART Registers ....................................................................................................................... 286
Figure 12.4-1
Transfer Data Formats in Asynchronous (Step-synchronous) Modes (Modes 0 and 1) ........ 298
Figure 12.4-2
Transfer Data Format in CLK Synchronous Mode (Mode 2) ................................................... 299
Figure 12.5-1
PE, ORE, FRE, and RDRF Flag Setting Timings in Mode 0 ................................................... 301
Figure 12.5-2
ORE, FRE, and RDRF Flag Setting Timings in Mode 1 .......................................................... 302
Figure 12.5-3
ORE and RDRF Flag Setting Timings in Mode 2 .................................................................... 302
Figure 12.5-4
TDRE Setting Timings in Modes 0 and 1 ................................................................................ 303
Figure 12.5-5
TDRE Setting Timing in Mode 2 .............................................................................................. 303
Figure 12.6-1
Example of System Construction in Mode 1 ............................................................................ 304
Figure 12.6-2
Communication Flowchart in Mode 1 ...................................................................................... 305
Figure 13.2-1
Block Diagram of the DMA Controller ...................................................................................... 309
Figure 13.3-1
Registers of the DMA Controller .............................................................................................. 310
Figure 13.4-1
Basic Operation Flow Chart of the DMA Controller ................................................................. 324
Figure 13.4-2
Burst Transfer Sequence ......................................................................................................... 326