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15.2 I-RAM Activation Sequence
This section explains the I-RAM activation sequence.
s I-RAM Activation Sequence
Precautions:
The I-RAM/ROM is directly connected to the instruction bus (I-bus) for high-speed
processing. Since the CPU recognizes data in the I-RAM/ROM as instructions, place only
an instruction set in the I-RAM/ROM. Executing a mode data write instruction changes the
address decoder to internal ROM mode.
Therefore, avoid placing this instruction and
subsequent instructions in an area (000B 8000H to 000B FFFFH) corresponding to the I-
RAM/ROM.
Do not place a standby instruction in the I-RAM/ROM.
Even after mode data is written, the I-RAM can be written by setting the IRMD bit in the
IRMC register. Although the I-RAM contents are free to change, be careful not to rewrite the
area under the current instruction access.
As described in 3.14, "Memory Access Mode," set the bus width with AMD0 to AMD5 before
setting mode data.
Instruction caching does not apply to the I-ROM/RAM.
1.
Set the mode pins (MD2 to MD0) to external vector mode.
Use the initial vector table placed in an external area. (Do not set the I-ROM/RAM
area.)
2.
After the initialize routine, set the IRMD bit in the IRMC register to 1 to disconnect the
I-RAM from the I-bus and connect it to the D-bus.
The CPU programmable I/O transfer or DMA transfer shifts a program from the
external area to the I-RAM. The program should be in the external ROM area. Since
the I-RAM is disconnected from the I-bus, using a program in the I-ROM/RAM area
may cause a loss of control.
For the I-RAM program transfer, write 000B C000H to 000B FFFFH (see 15.3, "I-
ROM/RAM Memory Mapping"). Be sure to read and write the I-RAM by half-word
access.
3.
At the end of program transfer, set the IRMD bit in the IRMC register to 0 to
disconnect the I-RAM from the D-bus and connect it to the I-bus. Then write mode
data to set the bus mode.
Set 01 (internal ROM/external bus) for the bus mode (M1, M0).
The I-RAM becomes valid only after mapped in the area from 000B C000H to 000B
FFFFH (see 15.3, "I-ROM/RAM Memory Mapping").
The I-ROM is valid for executing instructions only.
When using the I-RAM/ROM, set internal ROM/external bus mode.