421
INDEX
communication prescaler control register
(CDCR) ...................................................... 294
compare operation instruction.............................. 400
continuous transfer .............................................. 326
control register ..................................................... 263
control status register (ADCS) ............................. 271
control status register (TMCSR) .......................... 215
control/status register (PCNH/L) .......................... 229
converted data protection function....................... 279
coprocessor control instruction ............................ 417
counter operation status ...................................... 223
CPU architecture, feature of .................................. 28
cycle setting register (PCSR)............................... 232
D
DACK0/1/2 output timing ..................................... 344
data access.................................................... 49, 389
data bus width.............................................. 143, 150
data bus width and control signal, relationship
between ............................................. 139, 140
data format ................................................... 142, 148
data register (ADCR) ........................................... 276
dedicated register .................................................. 42
delay slot, branch instruction with .......................... 54
delay slot, limitation on operation of branch instruction
with ............................................................. 55
delay slot, operation of branch instruction with ...... 54
delayed branch instruction ................................... 406
delayed interrupt control register (DICR) ............. 249
delayed interrupt module, register of ................... 248
DEOP0/1/2 output timing ..................................... 344
detection result register (BSRR) .......................... 354
device handling note .............................................. 22
difference between little and big endian............... 148
direct addressing instruction ................................ 417
disabling all channel............................................. 337
DLYI bit in DCIR................................................... 250
DMA controller operation, outline of..................... 323
DMA controller, basic operation flow chart of ...... 323
DMA controller, block diagram of ......................... 309
DMA controller, common symbol of ..................... 323
DMA controller, hardware configuration of........... 308
DMA controller, main function of .......................... 308
DMA controller, register of ................................... 310
DMA request suppression register (PDRR) ........... 83
DMA suppression circuit, block diagram of ............ 92
DMA suppression function, setting ........................ 92
DMA transfer and interrupt................................... 333
DMA transfer start................................................ 335
DMA transfer, end of ............................................337
DMA transfer, pause of.........................................335
DMAC addressing/transfer count register
(DMACC) ....................................................317
DMAC control/status Register (DMACS)..............311
DMAC general control register (DMACR).............320
DMAC source/destination address register group
(DMASA, DMADA) .....................................322
DMAC transfer program, sample ..........................348
DMAC transfer, program specification for ............348
double or long-double variable, using...................387
DRAM connection.................................................139
DRAM control pin .................................................156
DRAM control register 4 and 5 (DMCR4 and
DMCR5) .....................................................128
DRAM device connection, example of..................159
DRAM interface ....................................................160
DRAM interface timing in high-speed page mode 183
DRAM refresh.......................................................162
DRAM signal control register (DSCR) ..................136
DREQ0/1/2 input timing for continuous transfer on
same channel ............................................343
duty setting register (PDUT) .................................232
E
each CPU state, pin status in ...............................379
each operation mode, cache status in ....................37
EIT source ..............................................................58
EIT source received and masking of other source,
priority of.......................................................68
EIT vector table ......................................................66
EIT, feature of.........................................................58
EIT, note on ............................................................59
EIT, return from ......................................................58
emulator/monitor debugger ..................................392
enable interrupt request register (ENIR)...............241
error stop ..............................................................337
external access, comparison of ............................139
external bus access..............................................144
external bus operation, program specification for.198
external bus operation, sample program for.........199
external bus request .............................................162
external device connection, example of .......147, 151
external event count .............................................221
external I/O device and external memory device,
transfer between.........................................346
external interrupt procedure .................................243
external interrupt processing ................................243
external interrupt request level .............................244