422
INDEX
external interrupt request register (EIRR) ............ 241
external interrupt/NMI control section, block diagram
of ................................................................ 240
external interrupt/NMI control section, register of. 240
external level register (ELVR) .............................. 242
external memory device, transfer between external
I/O device and ............................................ 346
external pin control register 0 (EPCR0)................ 133
external pin control register 1 (EPCR1)................ 135
external pin function (I/O port or Control Pin),
selection of ................................................ 207
external transfer request ...................................... 325
external wait cycle timing ..................................... 173
F
FPT-144-M08, outside dimension drawing of........... 8
FPT-144-M08, pin arrangement diagram of ............. 9
FR series instruction list ....................................... 399
FR series, common memory mapping of ............... 50
G
gear control register (GCR) .................................... 79
gear control section, block diagram of.................... 87
gear ratio, setting ................................................... 87
general-purpose register ........................................ 47
H
half-word access .................................................. 153
hardware configuration......................................... 263
high-speed page mode, DRAM interface timing
in ................................................................ 183
hold arbitration ..................................................... 333
hold request cancel request level setting register
(HRCL) ....................................................... 257
hold request cancel request sequence ................ 264
hold request cancel request, available level of..... 262
hold request, cancellation standard for ................ 262
hyper DRAM interface timing ............................... 192
hyper DRAM interface, read cycle timing of ......... 190
hyper DRAM interface, write cycle timing of......... 191
I
I flag ....................................................................... 60
I/O circuit type ........................................................ 17
I/O mapping.......................................................... 367
I/O mapping, reading............................................ 366
I/O port register .................................................... 204
I/O port, basic block diagram of ........................... 204
I-bus RAN control register (IRMC) ....................... 360
immediate value set and 16/32-bit immediate value
transfer instruction ..................................... 403
initial valued variable, placing .............................. 386
input negate timing of DREQ0/1/2 at continuous
transfer request stopping ........................... 342
input pin function (in internal clock mode)............ 221
instruction cache control register (ICHCR) ............ 35
instruction cache setting method ........................... 39
instruction cache tag, configuration of ................... 33
instruction cache, cacheable area of ..................... 31
instruction cache, configuration of ......................... 31
instruction format ................................................. 397
instruction list, reading ......................................... 393
instruction, outline of .............................................. 52
INT instruction, processing of ................................ 71
INTE instruction, processing of .............................. 71
inter-channel priority order ................................... 340
interface ............................................................... 115
internal architecture, structure of ........................... 29
internal clock multiplication .................................. 197
internal clock operation ........................................ 219
internal peripheral request ................................... 325
inter-register transfer instruction .......................... 404
interrupt control register (ICR) ....................... 62, 256
interrupt control register (ICR), mapping of............ 62
interrupt controller, block diagram of.................... 253
interrupt controller, hardware configuration of ..... 252
interrupt controller, main function of..................... 252
interrupt controller, register of .............................. 254
interrupt level ......................................................... 60
interrupt level mask register (ILM) ......................... 61
interrupt number................................................... 250
interrupt output..................................................... 339
interrupt resource, release of ............................... 260
interrupt stack ........................................................ 64
interrupt vector ..................................................... 375
interrupt/NMI level masking ................................... 61
I-RAM activation sequence .................................. 361
I-ROM/RAM memory mapping............................. 362
K
-K lib option, specifying ........................................ 387
L
limitation on operation of branch instruction with delay
slot ............................................................... 55
little and big endian, difference between.............. 148
little endian register (LER) ................................... 138
little-endian bus access........................................ 139