327
13.4 Operations of the DMA Controller
Figure 13.4-3 Continuous Transfer Sequence
[Features of continuous transfer]
The transfer request is checked at every unit of transfer. As long as the external input level
is on, this module does not clear the transfer request and continues transfer. If the external
input level changes, this module clears the request and stops transfer at a boundary
between units of transfer. This is repeated until the transfer is completed a specified number
of times.
The other operations are the same as those in burst transfer.
Precautions:
This product has a buffer between the internal and external interfaces. This buffer generates
a time difference between bus operations input or output at the external pin and those in the
DMAC circuit. Therefore, DMAC transfer may overrun even when DREQ is negated (DMA
data transfer in the buffer continues even after DREQ is negated.
s Step Transfer
Transfer is executed once only on a transfer request.
Figure 13.4.4 shows the step transfer sequence when the block size is set to 1.
Figure 13.4-4 Step Transfer Sequence
[Features of step transfer]
Once a transfer request has been received, this module executes one unit of transfer (byte,
half-word, or word) and clears the transfer request to complete the transfer (after returning
the bus privilege).
Any other request during transfer is ignored.
If a transfer request of a higher priority is received from another channel during transfer, this
module switches the channel at the end of transfer without releasing the bus privilege and
starts the next transfer. Therefore, the priority order in step transfer becomes significant only
when transfer requests are generated simultaneously.
s Block Transfer
Transfer is executed a specified number of times on a transfer request.
Figure 13.4.5 shows the block transfer sequence when the block size is set to other than 1 (2 in
this example).
CPU
SA
DA
SA
DA
SA
DA
CPU
SA
DA
04
03
02
01
Transfer request
Bus operation
Transfer count
CPU
SA
DA
CPU
SA
DA
CPU
02
01
00
Transfer request
Bus operation
Transfer count
Transfer end