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CHAPTER 12 UART
12.4.1 Asynchronous (Step-synchronous) Modes
UART handles data of the Non Return to Zero (NRZ) format only.
Data transfer always starts from the start bit (L-level data). After the specified number
of bits are transferred starting from the LSB, the data transfer ends at the stop bit (H-
level data). If an external clock is selected, always enter clock pulses.
s Transfer Data Formats in Asynchronous (Step-synchronous) Modes
Figure 12.4.1 shows the transfer data formats in asynchronous (step-synchronous) modes.
The data length can be set to 7 or 8 bits in normal mode (mode 0) but must always be 8 bits in
multiprocessor mode (mode 1). No parity can be added in multiprocessor mode. Instead, the
A/D bit is always added.
Figure 12.4-1 Transfer Data Formats in Asynchronous (Step-synchronous) Modes (Modes 0 and 1)
r Reception
Reception is always in progress when the RXE bit (bit 9) is 1.
If a start bit appears in the reception line, a frame of data is received in the SCR-specified data
format. Once a frame of data has been received and an error occurs, the RDRF flag (SSR bit
12) is set after an error flag setting. If the RIE bit (bit 9) is set to 1, a reception interrupt is
issued to the CPU.
Each flag in SSR should be checked.
Read the SIDR register if the
reception status is normal or execute necessary processing if abnormal.
The RDRF flag is cleared when the SIDR register is read.
r Transmission
When the TDRE flag (SSR bit 11) is 1, transmit data is written into the SODR register. When
TXE (SCR bit 8) is 1, data is transmitted.
When an internal clock is selected, data is output synchronously with SCK.
Data set in the SODR register is loaded to the transmission shift register and transmission
starts. Then the TDRE flag is set to 1 again to allow the setting of next transmit data. If TIE
(SSR bit 8) is 1, however, a transmission interrupt request is issued to the CPU for transmit data
to be set in the SODR register.
The TDRE flag is cleared once when data is set in the SODR register.
SCK
SI,SO
Start
LSB
MSB Stop
(Mode 0)
A/D Stop
(Mode 1)
Transfer data: 01001101B
SI is input asynchronously with SCK.