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CONTENTS
CHAPTER 1
OUTLINE OF MB91110 ................................................................................ 1
1.1
Features of MB91110 ............................................................................................................................ 2
1.2
Models of MB91110 ............................................................................................................................... 6
1.3
Block Diagram of MB91110 ................................................................................................................... 7
1.4
Outside Dimension Drawing .................................................................................................................. 8
1.5
Pin Arrangement Diagram ..................................................................................................................... 9
1.6
Explanations of the Pin Functions ....................................................................................................... 10
1.7
I/O Circuit Types .................................................................................................................................. 17
CHAPTER 2
DEVICE HANDLING NOTES ...................................................................... 21
2.1
Device Handling Notes ........................................................................................................................ 22
CHAPTER 3
CPU ............................................................................................................. 25
3.1
Memory Space ..................................................................................................................................... 26
3.2
CPU Architecture ................................................................................................................................. 28
3.3
Instruction Cache ................................................................................................................................. 31
3.3.1
Instruction Cache Control Register (ICHCR) .................................................................................. 35
3.3.2
Status in Each Operation Mode ...................................................................................................... 37
3.3.3
Instruction Cache Setting Method .................................................................................................. 39
3.4
Dedicated Registers ............................................................................................................................ 42
3.4.1
Program Status Register (PS) ........................................................................................................ 44
3.5
General-purpose Registers ................................................................................................................. 47
3.6
Data Structure ...................................................................................................................................... 48
3.7
Word Alignment ................................................................................................................................... 49
3.8
Memory Mapping ................................................................................................................................. 50
3.9
Outline of Instructions .......................................................................................................................... 52
3.9.1
Branch Instruction with Delay Slot .................................................................................................. 54
3.9.2
Branch Instruction with No Delay Slot ............................................................................................ 57
3.10 Exception, Interrupt, and Trap (EIT) .................................................................................................... 58
3.10.1 EIT Interrupt Level .......................................................................................................................... 60
3.10.2 Interrupt Control Register (ICR) ...................................................................................................... 62
3.10.3 System Stack Pointer (SSP) ........................................................................................................... 63
3.10.4 Interrupt Stack ................................................................................................................................ 64
3.10.5 Table Base Register (TBR) ............................................................................................................ 65
3.10.6 EIT vector table .............................................................................................................................. 66
3.10.7 Multi-EIT Processing ...................................................................................................................... 68
3.10.8 EIT Processing ............................................................................................................................... 70
3.11 Reset Sequence .................................................................................................................................. 73
3.12 Clock .................................................................................................................................................... 74
3.12.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) .......................... 76
3.12.2 Timebase Timer Clear Register (CTBR) ........................................................................................ 78
3.12.3 Gear Control Register (GCR) ......................................................................................................... 79
3.12.4
Watchdog Reset Defer Register (WPR) ........................................................................................ 82
3.12.5 DMA Request Suppression Register (PDRR) ................................................................................ 83