![](http://datasheet.mmic.net.cn/120000/MB-91110PMT2_datasheet_3559008/MB-91110PMT2_185.png)
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4.5 Bus Timing
r Ordinary DRAM interface
The ordinary DRAM interface is a bus interface mode where CAS access is made in two clock
cycles. For this mode, set both the DSAS and HYPR bits to 0 in DMCR4 or DMCR5. In this
mode, five clock cycles are the basic cycle both for read and write. The cycles are expressed
as Q1 to Q5 in this guide.
High-speed mode can be set using the PAGE bit in DMCR4 or DMCR5.
In this mode, the column address and CAS control ensure high-speed memory access in the
same page space where row addresses match. To use this mode, the PAGE bit in DMCR4 or
DMCR5 should be set to 1.
Bits PGS3 to PGS1 in DMCR4 or DMCR5 are checked to see whether access is within the
same page.
Access in high-speed page mode starts when ordinary access by Q1 to Q5 is finished. When
high-speed page mode starts, the cycles of Q4 and Q5 are repeated. Once this mode has been
set, RAS remains low until access outside a page or a refresh cycle is generated.
The Q1 and Q4 wait cycles can be set even in high-speed page mode. When high-speed page
mode starts, the cycles of Q4, Q4W, and Q5 are repeated.
Read cycle of ordinary DRAM interface
Write cycle of ordinary DRAM interface
Ordinary DRAM read cycle
Ordinary DRAM write cycle
Automatic wait cycle in ordinary DRAM interface
DRAM interface in high-speed page mode
r Single DRAM interface
The single DRAM interface is a bus interface mode where CAS access is made in one clock
cycle. For this mode, set the DSAS bit to 1 and the HYPR bit to 0 in DMCR4 or DMCR5. When
using this mode, set the PAGE bit to 1 in DMCR4 or DMCR5 to activate high-speed page mode.
The single DRAM interface starts up at the rise of Q1 to Q3 cycles like the ordinary DRAM
interface. Once the Q4 cycle has started, one-cycle CAS control is executed in one cycle for
read or write. In this guide, the Q4 cycle is expressed as Q4SR for read and Q4SW for write.
The page size, 1CAS/2WE or 2CAS/1WE setting, and Q1-cycle wait are the same those for the
ordinary DRAM interface.
Read cycle of single DRAM interface
Write cycle of single DRAM interface
Single DRAM interface
r Hyper DRAM interface
The hyper DRAM interface is a bus interface mode where CAS access is made in one clock
cycle. In this mode, data is fetched at a read cycle to set the next address one step earlier for
high-speed DRAM access. For this mode, set both the DSAS and HYPR bits to 1 in DMCR4 or
DMCR5. When using this mode, set the PAGE bit to 1 in DMCR4 or DMCR5 to activate high-
speed page mode.
The hyper DRAM interface starts up at the rise of Q1 to Q3 cycles like the ordinary DRAM
interface. Once the Q4 cycle has started, one-cycle CAS control is executed in one cycle for
read or write. In this guide, the Q4 cycle is expressed as Q4HR for read and Q4HW for write.
The page size, 1CAS/2WE or 2CAS/1WE setting, and Q1-cycle wait are the same those for the