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CHAPTER 3 CPU
Figure 3.2-2 Instruction Pipeline
Instructions are always executed in a particular order. If instruction A enters the pipeline before
instruction B, instruction A attains the write-back stage before instruction B.
As a rule, instructions are executed at the speed of one instruction per cycle. However, several
cycles are necessary for a load/store instruction with a memory wait, a branch instruction with
no delayed slot, or a multi-cycle instruction. The instruction execution speed also decreases if
instructions are supplied slowly.
For details on the instructions, see 3. 9, "Outline of Instructions."
r Instruction cache
The on-chip instruction cache enables a high-performance system to be constructed without
extra costs on the external high-speed memory and its control logic. Even if the external bus
speed is slow, instructions can be supplied to the CPU at high speed.
For details on the instructions, see 3. 3, "Instruction Cache."
r 32-bit <----> 16-bit bus converter
This converter interfaces 32-bit D-bus and 16-bit R-bus to realize access from the CPU to the
internal peripheral circuits. Some of the internal circuits are limited in terms of access width.
If the CPU makes 32-bit access, this bus converter converts the access into two 16-bit accesses
to the R-bus. The access width is limited on some internal peripheral circuits.
r Harvard <----> Princeton bus converter
This converter coordinates CPU instruction access and data access to realize a smooth
interface with an external bus.
The CPU has the Harvard architecture of an instruction bus and a data bus, while the bus
controller for external bus control has the Princeton architecture of a single bus.
This bus
converter gives priorities to CPU instruction access and data access to control access to the
bus controller. This function always optimizes the external bus access order.
This converter has a two-word write buffer to eliminate the CPU bus wait time and a one-word
prefetch buffer to fetch an instruction.