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3.12.6 PLL Control Register (PCTR) ........................................................................................................ 84
3.12.7 Watchdog Function ........................................................................................................................ 85
3.12.8 Gear Function ................................................................................................................................ 87
3.12.9 Reset Source Hold Function .......................................................................................................... 90
3.12.10 DMA Suppression Function ........................................................................................................... 92
3.12.11 Clock Doubler Function ................................................................................................................. 94
3.12.12 Example of PLL Clock Setting ....................................................................................................... 96
3.13 Low-power Consumption .................................................................................................................. 100
3.13.1 Standby Control Register (STCR) ................................................................................................ 102
3.13.2 Stop Status .................................................................................................................................. 103
3.13.3 Sleep Status ................................................................................................................................ 106
3.13.4 Status Transition in Low-power Consumption Mode ................................................................... 108
3.14 Memory Access Modes ..................................................................................................................... 109
CHAPTER 4
BUS INTERFACE ..................................................................................... 113
4.1
Outline of the Bus Interface .............................................................................................................. 114
4.2
Block Diagram of the Bus Interface .................................................................................................. 117
4.3
Bus Interface Registers ..................................................................................................................... 118
4.3.1
Area Selection Register (ASR) and Area Mask Register (AMR) ................................................. 119
4.3.2
Area Mode Register 0 (AMD0) ..................................................................................................... 122
4.3.3
Area Mode Register 1 (AMD1) ..................................................................................................... 124
4.3.4
Area Mode Register 32 (AMD32) ................................................................................................. 125
4.3.5
Area Mode Register 4 (AMD4) ..................................................................................................... 126
4.3.6
Area Mode Register 5 (AMD5) ..................................................................................................... 127
4.3.7
DRAM Control Registers 4 and 5 (DMCR4 and DMCR5) ............................................................ 128
4.3.8
Refresh Control Register (RFCR) ................................................................................................ 131
4.3.9
External Pin Control Register 0 (EPCR0) .................................................................................... 133
4.3.10 External Pin Control Register 1 (EPCR1) .................................................................................... 135
4.3.11 DRAM Signal Control Register (DSCR) ....................................................................................... 136
4.3.12 Little Endian Register (LER) ........................................................................................................ 138
4.4
Bus Operations ................................................................................................................................. 139
4.4.1
Relationships between Data Bus Widths and Control Signals ..................................................... 140
4.4.2
Big-endian Bus Access ................................................................................................................ 142
4.4.3
Little-endian Bus Access ............................................................................................................. 148
4.4.4
Comparison of External Accesses in Big and Little Endian Modes ............................................. 152
4.4.5
DRAM Connection ....................................................................................................................... 156
4.5
Bus Timing ........................................................................................................................................ 160
4.5.1
Basic Read Cycle ........................................................................................................................ 163
4.5.2
Basic Write Cycle ......................................................................................................................... 165
4.5.3
Read Cycle in Each Mode ........................................................................................................... 167
4.5.4
Write Cycle In Each Mode ........................................................................................................... 169
4.5.5
Read-write Cycle ......................................................................................................................... 171
4.5.6
Automatic Wait Cycle ................................................................................................................... 172
4.5.7
External Wait Cycle ..................................................................................................................... 173
4.5.8
Ordinary DRAM Interface Read Cycle ......................................................................................... 174
4.5.9
Ordinary DRAM Interface Write Cycle ......................................................................................... 176
4.5.10 Ordinary DRAM Read Cycle ........................................................................................................ 178
4.5.11 Ordinary DRAM Write Cycle ........................................................................................................ 180
4.5.12 Automatic Wait Cycle in the Ordinary DRAM Interface ................................................................ 182