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3.3 Instruction Cache
3.3.1
Instruction Cache Control Register (ICHCR)
The instruction cache control register (ICHCR) controls the instruction cache
operation, Writing this register does not affect the caching of an instruction fetched
within three cycles.
s Instruction Cache Control Register (ICHCR)
The instruction cache control register (ICHCR) is shared between ways 1 and 2.
Figure 3.3-3 Instruction Cache Control Register (ICHCR)
Bit 5: Global Lock (GBLK)
All the current entries are locked in cache.
When the bit value is 1, valid entries in cache are not updated at a cache miss.
However, an invalid sub-block is updated. The instruction data fetch operation is the same
as when the current entries are not locked.
Even when the global lock is on, one cycle is spent for a penalty at a cache miss.
Bit 4: Auto Lock Fil (ALFL)
A lock attempt on entries already locked sets this bit to 1.
If entry update is attempted on entries already locked in the entry auto lock status, new
entries are not locked in cache as intended by the user. This bit is referenced for debugging
this kind of program.
Writing 0 clears this bit.
Bit 3: Entry Auto Lock (EOLK)
This bit enables or disables auto locking for each entry in the instruction cache.
If entry access ends in a miss when this bit is 1, the entry lock bit in the cache tag is set to 1
by hardware to lock the entry. The entry once locked will not be updated even in the case of
a cache miss.
However, an invalid sub-block is updated. For secure locking, set this bit after flashing.
Bit 2: Entry Unlock (ELKR)
This bit clears the Entry Lock bit in all cache tags. When this bit is set to 1, the Entry Lock bit
is cleared to 0 in all cache tags at the next cycle. However, the contents of this bit are held
for one clock cycle only. For the second or later clock cycle, this bit is cleared.
07
06
05
04
03
02
01
00
Initial value Access
Address :
0000
GBLK ALFL
EOLK ELKR FLSH ENAB
--000000
Global lock
Auto lock fail
Entry auto lock
Entry unlock
Flash
Enable
H