v
READING THIS MANUAL
s Page Layout
In this manual, the content of each section is summarized immediately below the title. You can
obtain an outline of this product by reading through these summaries.
Also, higher section headings are given in lower sections so that you can know to which section
the text currently belongs.
s Terms
The following terms are used in this manual:
Term
Explanation
I-BUS
16-bit internal instruction bus: The instruction bus is independent of the data
bus in the FR30 Series because the internal Harvard architecture is adopted.
An instruction cache and a switch (arbiter) are connected to this bus.
D-BUS
32-bit internal data bus: Internal buses are connected to this bus.
C-BUS
Internal multiplexer bus: This bus is connected to I-bus and D-bus through a
switch. An external interface module is connected to this bus. Data and
instructions are multiplexed on the external data bus.
R-BUS
16-bit internal data bus: This bus is connected to D-bus through an adapter.
An I/O resource, clock generator, or interrupt controller is connected to this bus.
Since R-bus is 16 bits wide and data and addresses are multiplexed, it takes
several cycles for the CPU to access the resources.
E-unit
Arithmetic operation unit
φ
System clock signal output from the clock generator to an internal resource
connected to the R-bus. The fastest cycle of this signal is equal to the
oscillation cycle. However, the cycle is divided as 1/1, 1/2, 1/4, and 1/8 (or 1/2,
1/4, 1/8, and 1/16) depending on the setting of the PCK1 and PCK0 bits in the
GCR register of the clock generator.
θ
System clock signal serving as an operation clock for a resource connected to a
bus other than R-bus and also for the CPU. The fastest cycle of this signal is
equal to the oscillation cycle. However the cycle is divided as 1/1, 1/2, 1/4, and
1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0
bits in the GCR register of the clock generator.