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| 型号： | MCC68HC711D3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC |
| 封装： | DIE |
| 文件页数： | 110/157页 |
| 文件大小： | 2252K |
| 代理商： | MCC68HC711D3 |
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Resets, Interrupts, and Low-Power Modes
Data Sheet
MC68HC711D3 — Rev. 2
56
Resets, Interrupts, and Low-Power Modes
MOTOROLA
4.3.1 Software Interrupt (SWI)
The SWI is executed the same as any other instruction and takes precedence over
interrupts only if the other interrupts are masked (with I and X bits in the CCR set).
SWI execution is similar to that of the maskable interrupts in that it sets the I bit,
stacks the central processor unit (CPU) registers, etc.
NOTE:
The SWI instruction cannot be executed as long as another interrupt is pending.
However, once the SWI instruction has begun, no other interrupt can be honored
until the first instruction in the SWI service routine is completed.
4.3.2 Illegal Opcode Trap
Since not all possible opcodes or opcode sequences are defined, an illegal opcode
detection circuit has been included in the MCU. When an illegal opcode is
detected, an interrupt is required to the illegal opcode vector. The illegal opcode
vector should never be left uninitialized.
4.3.3 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) provides a programmable periodic interrupt. This
interrupt is maskable by either the I bit in the CCR or the RTI enable (RTII) bit of
the timer interrupt mask register 2 (TMSK2). The rate is based on the MCU E clock
and is software selectable to the E
÷ 213, E ÷ 214, E ÷ 215, or E ÷ 216. See PACTL,
TMSK2, and TFLG2 register descriptions in Section 8. Programmable Timer for
control and status bit information.
4.3.4 Interrupt Mask Bits in the CCR
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable
interrupts and XIRQ. After minimum system initialization, software may clear the X
bit by a TAP instruction, thus enabling XIRQ interrupts. Thereafter software cannot
set the X bit. So, an XIRQ interrupt is effectively a non-maskable interrupt. Since
the operation of the I bit related interrupt structure has no effect on the X bit, the
internal XIRQ pin remains effectively non-masked. In the interrupt priority logic, the
XIRQ interrupt is a higher priority than any source that is maskable by the I bit. All
I bit related interrupts operate normally with their own priority relationship.
When an I bit related interrupt occurs, the I bit is automatically set by hardware after
stacking the CCR byte. The X bit is not affected. When an X bit related interrupt
occurs, both the X and the I bit are automatically set by hardware after stacking the
CCR. A return-from-interrupt (RTI) instruction restores the X and I bits to their
preinterrupt request state.
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