参数资料
型号: MCC68HC711D3
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封装: DIE
文件页数: 7/157页
文件大小: 2252K
代理商: MCC68HC711D3
Programmable Timer
Data Sheet
MC68HC711D3 — Rev. 2
104
Programmable Timer
MOTOROLA
8.4.2 Timer Compare Force Register
The timer compare force register (CFORC) allows forced early compares.
FOC1–FOC5 correspond to the five output compares. These bits are set for each
output compare that is to be forced. The action taken as a result of a forced
compare is the same as if there were a match between the OCx register and the
free-running counter, except that the corresponding interrupt status flag bits are not
set. The forced channels trigger their programmed pin actions to occur at the next
timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is
programmed to toggle its output on a successful compare because a normal
compare that occurs immediately before or after the force can result in an
undesirable operation.
FOC1–FOC5 — Write 1s to Force Compare Bits
0 = Not affected
1 = Output x action occurs
Bits 2–0 — Not implemented, always read 0.
Address: $001B — TOC3 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
11111111
Address: $001C — TOC4 (High)
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
11111111
Address: $001D — TOC4 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:
11111111
Figure 8-6. Timer Output Capture Registers (TOCx) (Continued)
Address:
$000B
Bit 7
654321
Bit 0
Read:
FOC1
FOC2
FOC3
FOC4
FOC5
0
Write:
Reset:
00000000
Figure 8-7. Timer Compare Force Register (CFORC)
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