参数资料
型号: MCC68HC711D3
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封装: DIE
文件页数: 33/157页
文件大小: 2252K
代理商: MCC68HC711D3
Electrical Characteristics
Data Sheet
MC68HC711D3 — Rev. 2
128
Electrical Characteristics
MOTOROLA
9.8 Expansion Bus Timing
Num
Characteristic(1)
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min Max Min Max
Frequency of operation (E-clock frequency)
fO
dc
1.0
dc
2.0
dc
3.0
MHz
1
Cycle time
tcyc
1000
500
333
ns
2
Pulse width, E low, PWEL = 1/2 tcyc — 23 ns
PWEL
477
227
146
ns
3
Pulse width, E high, PWEH = 1/2 tcyc – 28 ns
PWEH
472
222
141
ns
4A
E and AS rise time
tr
—20
20
20
ns
4B
E and AS fall time
tf
—20
20
15
ns
9
Address hold time(2)a, tAH = 1/8 tcyc – 29.5 ns
tAH
95.5
33
26
ns
12
Non-muxed address valid time to E rise
tAV = PWEL – (tASD + 80 ns)
(2)a
tAV
281.5
94
54
ns
17
Read data setup time
tDSR
30
30
30
ns
18
Read data hold time (max = tMAD)tDHR
0
145.5
0
83
0
51
ns
19
Write data delay time, tDDW = 1/8 tcyc + 65.5 ns
(2)a
tDDW
190.5
128
71
ns
21
Write data hold time, tDHW = 1/8 tcyc – 29.5 ns
(2)a
tDHW
95.5
33
26
ns
22
Muxed address valid time to E rise
tAVM = PWEL – (tASD + 90 ns)
(2)a
tAVM
271.5
84
54
ns
24
Muxed address valid time to AS fall
tASL = PWASH – 70 ns
tASL
151
26
13
ns
25
Muxed address hold time, tAHL = 1/8 tcyc – 29.5 ns
(2)b
tAHL
95.5
33
31
ns
26
Delay time, E to AS rise, tASD = 1/8 tcyc – 9.5 ns
(2)a
tASD
115.5
53
31
ns
27
Pulse width, AS high, PWASH = 1/4 tcyc – 29 ns
PWASH
221
96
63
ns
28
Delay time, AS to E rise, tASED = 1/8 tcyc – 9.5 ns
(2)b
tASED
115.5
53
31
ns
29
MPU address access time(2)a
tACCA = tcyc – (PWEL– tAVM) – tDSR – tf
tACCA
744.5
307
196
ns
35
MPU access time , tACCE = PWEH – tDSR
tACCE
442
192
111
ns
36
Muxed address delay (previous cycle MPU read)
tMAD = tASD + 30 ns
(2)a(3)
tMAD
145.5
83
51
ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYC in the above formulas, where applicable:
(a) (1-dc)
× 1/4 t
CYC
(b) dc
× 1/4 t
CYC
Where:
DC is the decimal value of duty cycle percentage (high time).
3. Formula only for dc to 2 MHz.
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