收藏本站
参数资料
型号： MCC68HC711D3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封装： DIE
文件页数： 93/157页
文件大小： 2252K
代理商： MCC68HC711D3
Central Processor Unit (CPU)
Data Sheet
MC68HC711D3 — Rev. 2
40
Central Processor Unit (CPU)
MOTOROLA
3.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation
is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative
if its most significant bit (MSB) is a 1. A quick way to test whether the contents of a
memory location has the MSB set is to load it into an accumulator and then check
the status of the N bit.
3.2.6.5 I-Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable
interrupt sources. While the I bit is set, interrupts can become pending, but the
operation of the CPU continues uninterrupted until the I bit is cleared. After any
reset, the I bit is set by default and can be cleared only by a software instruction.
When an interrupt is recognized, the I bit is set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I bit is 0 after
a return from interrupt is executed. Although the I bit can be cleared within an
interrupt service routine, "nesting" interrupts in this way should be done only when
there is a clear understanding of latency and of the arbitration mechanism. Refer
to Section 4. Resets, Interrupts, and Low-Power Modes.
3.2.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic
unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half
carry is used during BCD operations.
3.2.6.7 X-Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is
set by default and must be cleared by a software instruction. When an XIRQ
interrupt is recognized, the X and I bits are set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, an RTI
instruction is normally executed, causing the registers to be restored to the values
that were present before the interrupt occurred. The X interrupt mask bit is set only
by hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value
loaded into the CCR from the stack has been cleared). There is no hardware action
for clearing X.
3.2.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop condition. If the STOP instruction is encountered
by the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction,
相关PDF资料
PDF描述
MC68HC711D3MP2 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40
MC68HC711D3S 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP40
MC68HC711D3FN 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC711G5CFN 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84
MC68HC11G7CFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84
相关代理商/技术参数
参数描述
MCC68HRC705JP7 制造商:Motorola Inc 功能描述:
MCC6M10 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 6SQMM M10 STUD
MCC6M3 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 6SQMM M3 STUD
MCC6M3.5 制造商:Thomas & Betts 功能描述:METRIC CU CONNECTOR 6SQMM 3.5 STUD
MCC6M4 制造商:Thomas & Betts 功能描述:METRIC CONNECTOR 6SQMM M4 STUD
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*