参数资料
型号: MCC68HC711D3
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封装: DIE
文件页数: 15/157页
文件大小: 2252K
代理商: MCC68HC711D3
Programmable Timer
Real-Time Interrupt
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Programmable Timer
111
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits 3–2 — Unimplemented
Always read 0.
PR1 and PR0 — Timer Prescaler Select Bits
Refer to Table 8-4.
NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable
the corresponding interrupt sources.
8.5.2 Timer Interrupt Flag 2 Register
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer
system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2
allow the timer subsystem to operate in either a polled or interrupt driven system.
Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To
clear RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Always read 0.
Address:
$0025
Bit 7
654321
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
0000
Write:
Reset:
00000000
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
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