参数资料
型号: MCC68HC711D3
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, UUC
封装: DIE
文件页数: 119/157页
文件大小: 2252K
代理商: MCC68HC711D3
Resets, Interrupts, and Low-Power Modes
Data Sheet
MC68HC711D3 — Rev. 2
64
Resets, Interrupts, and Low-Power Modes
MOTOROLA
IRVNE — Internal Read Visibility/Not E
This bit may be read at any time. It may be written once in any mode. IRVNE is
set during reset in special test mode only, and cleared by reset in the other
modes.
1 = Data from internal reads is driven out on the external data bus in
expanded modes.
0 = Data from internal reads is not visible on the external data bus.
As shown in the table, in single-chip and bootstrap modes IRVNE determines
whether the E clock is driven out or forced low.
1 = E pin driven low
0 = E clock driven out of the chip
NOTE:
To prevent bus conflicts, when using internal read visibility, the user must disable
all external devices from driving the data bus during any internal access.
PSEL3–PSEL0 — Priority Selects
These four bits are used to specify one I bit related interrupt source, which then
becomes the highest priority I bit related interrupt source. These bits may be
written only while the I bit in the CCR is set, inhibiting I bit related interrupts. An
interpretation of the value of these bits is shown in Table 4-4.
During reset, PSEL3–PSEL0 are initialized to 0101, which corresponds to
reserved (default to IRQ). IRQ becomes the highest priority I bit related interrupt
source.
Mode
IRVNE
Out
of Reset
E Clock
Out
of Reset
IRV
Out
of Reset
IRVNE
Affects
Only
IRVNE
May
be Written
Single chip
0
On
Off
E
Once
Expanded multiplexed
0
On
Off
IRV
Once
Bootstrap
0
On
Off
E
Once
Special test
1
On
IRV
Once
Table 4-4. Highest Priority Interrupt Selection
PSEL3–PSEL0
Interrupt Source Promoted
0 0 0 0
Timer overflow
0 0 0 1
Pulse accumulator overflow
0 0 1 0
Pulse accumulator input edge
0 0 1 1
SPI serial transfer complete
0 1 0 0
SCI serial system
0 1 0 1
Reserved (default to IRQ)
0 1 1 0
IRQ (external pin)
0 1 1 1
Real-time interrupt
1 0 0 0
Timer input capture 1
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