MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI)
87
Data Sheet — MC68HC711D3
Section 7. Serial Peripheral Interface (SPI)
7.1 Introduction
The serial peripheral interface (SPI), an independent serial communications
subsystem, allows the microcontroller unit (MCU) to communicate synchronously
with peripheral devices, such as:
Transistor-transistor logic (TTL) shift registers
Liquid crystal diode (LCD) display drivers
Analog-to-digital converter (ADC) subsystems
Other microprocessors (MCUs)
The SPI is also capable of inter-processor communication in a multiple master
system. The SPI system can be configured as either a master or a slave device
with data rates as high as one half of the E-clock rate when configured as master,
and as fast as the E-clock rate when configured as slave.
7.2 Functional Description
The central element in the SPI system is the block containing the shift register and
the read data buffer. The system is single buffered in the transmit direction and
double buffered in the receive direction. This means that new data for transmission
cannot be written to the shifter until the previous transfer is complete; however,
received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read out of the
read data buffer before the next serial character is ready to be transferred, no
overrun condition occurs. A single MCU register address is used for reading data
from the read data buffer, and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write
collision, and mode fault) performed by the serial peripheral status register (SPSR).
The SPI control block represents those functions that control the SPI system
through the serial peripheral control register (SPCR).
Refer to Figure 7-1, which shows the SPI block diagram.