
Central Processor Unit (CPU)
Instruction Set
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
43
3.5.6 Relative
The relative addressing mode is used only for branch instructions. If the branch
condition is true, an 8-bit signed offset included in the instruction is added to the
contents of the program counter to form the effective branch address. Otherwise,
control proceeds to the next instruction. These are usually 2-byte instructions.
3.6 Instruction Set
Refer to Table 3-2, which shows all the M68HC11 instructions in all possible
addressing modes. For each instruction, the table shows the operand construction,
the number of machine code bytes, and execution time in CPU E-clock cycles.
Table 3-2. Instruction Set (Sheet 1 of 8)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
ABA
Add
Accumulators
A + B
AINH
1B
—
2
—
—
ABX
Add B to X
IX + (00 : B)
IX
INH
3A
—
3
—
——
———
——
ABY
Add B to Y
IY + (00 : B)
IY
INH
18
3A
—
4
—
——
———
——
ADCA (opr)
Add with Carry
to A
A + M + C
AA
IMM
ADIR
AEXT
AIND,X
AIND,Y
89
99
B9
A9
18
A9
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADCB (opr)
Add with Carry
to B
B + M + C
BB
IMM
BDIR
BEXT
BIND,X
BIND,Y
C9
D9
F9
E9
18
E9
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADDA (opr)
Add Memory to
A
A + M
A
A
IMM
ADIR
AEXT
AIND,X
AIND,Y
8B
9B
BB
AB
18
AB
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADDB (opr)
Add Memory to
B
B + M
BB
IMM
BDIR
BEXT
BIND,X
BIND,Y
CB
DB
FB
EB
18
EB
ii
dd
hh
ll
ff
2
3
4
5
——
—
ADDD (opr)
Add 16-Bit to D
D + (M : M + 1)
DIMM
DIR
EXT
IND,X
IND,Y
C3
D3
F3
E3
18
E3
jj
kk
dd
hh
ll
ff
4
5
6
7
——
ANDA (opr)
AND A with
Memory
A M
AA
IMM
A
DIR
A
EXT
AIND,X
AIND,Y
84
94
B4
A4
18
A4
ii
dd
hh
ll
ff
2
3
4
5
——
0—
ANDB (opr)
AND B with
Memory
B M
BB
IMM
BDIR
BEXT
BIND,X
BIND,Y
C4
D4
F4
E4
18
E4
ii
dd
hh
ll
ff
2
3
4
5
——
0—
ASL (opr)
Arithmetic Shift
Left
EXT
IND,X
IND,Y
78
68
18
68
hh
ll
ff
6
7
——
C
0
b7
b0