![](http://datasheet.mmic.net.cn/120000/MC68HC711D3MFN3_datasheet_3559540/MC68HC711D3MFN3_97.png)
Programmable Timer
Timer Structure
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Programmable Timer
97
The COP watchdog clock input (E
÷215) is tapped off of the free-running counter
chain. The COP automatically times out unless it is serviced within a specific time
by a program reset sequence. If the COP is allowed to time out, a reset is
generated, which drives the RESET pin low to reset the MCU and the external
system. Refer to Table 8-1 for crystal related frequencies and periods.
8.2 Timer Structure
Figure 8-2 shows the capture/compare system block diagram. The port A pin
control block includes logic for timer functions and for general-purpose input/output
(I/O). For pins PA2, PA1, and PA0, this block contains both the edge-detection
logic and the control logic that enables the selection of which edge triggers an input
capture. The digital level on PA2–PA0 can be read at any time (read PORTA
register), even if the pin is being used for the input capture function. Pins PA6–PA4
are used for either general-purpose output or as output compare pins. Pin PA3 can
be used for general-purpose I/O, input capture 4, output compare 5, or output
compare 1. When one of these pins is being used for an output compare function,
it cannot be written directly as if it were a general-purpose output. Each of the
output compare functions (OC5–OC2) is related to one of the port A output pins.
Output compare 1 (OC1) has extra control logic, allowing it optional control of any
combination of the PA7–PA3 pins. The PA7 pin can be used as a general-purpose
I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.
Table 8-1. Timer Summary
Control
Bits
XTAL Frequencies
4.0 MHz
8.0 MHz
12.0 MHz
Other Rates
1.0 MHz
2.0 MHz
3.0 MHz
(E)
1000 ns
500 ns
333 ns
(1/E)
PR1 and PR0
Main Timer Count Rates
0 0
1 count —
overflow —
1.0 s
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
(E/1)
(E/216)
0 1
1 count —
overflow —
4.0 s
262.14 ms
2.0 s
131.07 ms
1.333 s
87.381 ms
(E/4)
(E/218)
1 0
1 count —
overflow —
8.0 s
524.29 ms
4.0 s
262.14 ms
2.667 s
174.76 ms
(E/8)
(E/219)
1 1
1 count —
overflow —
16.0 s
1.049 s
8.0 s
524.29 ms
5.333 s
349.52 ms
(E/16)
(E/220)