参数资料
型号: MT45W1MW16BDGB-708 AT
厂商: Micron Technology Inc
文件页数: 10/59页
文件大小: 0K
描述: IC PSRAM 16MBIT 104MHZ 54VFBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: PSRAM(页)
存储容量: 16M (1M x 16)
速度: 70ns
接口: 并联
电源电压: 1.7 V ~ 1.95 V
工作温度: -40°C ~ 105°C
封装/外壳: 54-VFBGA
供应商设备封装: 54-VFBGA(6x8)
包装: 托盘
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Functional Description
Functional Description
In general, the MT45W1MW16BDGB devices are high-density alternatives to SRAM and
Pseudo SRAM products, popular in low-power, portable applications.
The MT45W1MW16BDGB contains a 16,777,216-bit DRAM core organized as 1,048,576
addresses by 16 bits. This device implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their default
settings (see Figure 17 on page 23 and Figure 22 on page 27). V CC and V CC Q must be
applied simultaneously. When they reach a stable level at or above 1.7V, the device will
require 150μs to complete its self-initialization process. During the initialization period,
CE# should remain HIGH. When initialization is complete, the device is ready for
normal operation.
Figure 4:
Power-Up Initialization Timing
V cc = 1.7V
V cc
tPU > 150μs
Devi c e rea d y for
V cc Q
Devi c e Initialization normal operation
Bus Operating Modes
The MT45W1MW16BDGB CellularRAM products incorporate a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode, and burst mode read and write transfers. The
specific interface supported is defined by the value loaded into the bus configuration
register. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has
elapsed. WRITE operations (Figure 6 on page 11) occur when CE#, WE#, and LB#/UB#
are driven LOW. During asynchronous WRITE operations, the OE# level is a “Don't
Care,” and WE# will override OE#. The data to be written is latched on the rising edge of
CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode
disabled) can either use the ADV input to latch the address, or ADV can be driven LOW
during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT
will be driven while the device is enabled and its state should be ignored. WE# LOW time
must be limited to t CEM.
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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