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参数资料
| 型号： | MT46V32M8P-75ELIT:G |
| 元件分类： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.40 INCH, LEAD FREE,PLASTIC, TSOP-66 |
| 文件页数： | 32/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
36
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
17. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self
refresh mode, VREF must be powered within specified range. Exception: during the
period before VREF stabilizes, CKE < 0.3 × VDD is recognized as LOW.
18. The output timing reference level, as measured at the timing reference point (indi-
19. tHZ and tLZ transitions occur in the same access time windows as data valid transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (High-Z) or begins driving (Low-Z).
20. The intent of the “Don’t Care” state after completion of the postamble is the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN) then it must not transition LOW (below
VIH[DC] prior to tDQSH [MIN]).
21. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
24. The refresh period is 64ms (commerial and industrial) or 16ms (automotive). This
equates to an average refresh rate of 7.8125s (commercial and industrial) or 1.95us
(automotive). However, an AUTO REFRESH command must be asserted at least once
every 70.3s(commerial and industrial) or 17.55s (automotive); burst refreshing or
posting by the DRAM controller greater than 8 REFRESH cycles is not allowed.
25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
26. The data valid window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-
tion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio. The data valid window derating
curves are provided in Figure 12 on page 37 for duty cycles ranging between 50/50
and 45/55.
27. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15.
28. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during the REFRESH command period (tRFC [MIN]), else CKE is LOW (that is, during
standby).
29. To maintain a valid level, the transitioning edge of the input must:
29a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
29b. Reach at least the target AC level.
29c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M8T66ADC1 | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V32M8TG-5B/G | 制造商:Micron Technology Inc 功能描述:DRAM Chip DDR SDRAM 256M-Bit 32Mx8 2.6V 66-Pin TSOP Tray |
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