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参数资料
| 型号： | MT46V32M8P-75ELIT:G |
| 元件分类： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.40 INCH, LEAD FREE,PLASTIC, TSOP-66 |
| 文件页数： | 53/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
55
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific DDR SDRAM mode of operation. This
definition includes the selection of a burst length, a burst type, a CAS latency, and an
operating mode, as shown in Figure 23. The mode register is programmed via the LMR
command (with BA0=0 and BA1=0) and will retain the stored information until it is
programmed again or until the device loses power (except for bit A8, which is self-
clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–An specify the operating
mode.
Figure 23:
Mode Register Definition
Notes:
1. n is the most significant row address bit from Table 2 on page 2.
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3 (-5B only)
Reserved
2.5
Reserved
Burst length
CAS Latency BT
0
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode register
(Mx)
Address bus
97
6
5
4
3
8
21
0
M3
0
1
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
Operating mode
. . .
An
BA0
BA1
. . .
n1
n + 1
0
n + 2
Operating Mode
Normal operation
Normal operation/reset DLL
All other states reserved
M8
0
1
–
M9
0
–
. . .
0
–
Mn
0
–
M7
0
–
M6–M0
Valid
–
Burst Length
Reserved
2
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
Mn + 1
0
1
0
1
Mode Register Definition
Base mode register
Extended mode register
Reserved
Mn + 2
0
0
1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M8T66ADC1 | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V32M8TG-5B/G | 制造商:Micron Technology Inc 功能描述:DRAM Chip DDR SDRAM 256M-Bit 32Mx8 2.6V 66-Pin TSOP Tray |
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