参数资料
型号: MT46V32M8P-75ELIT:G
元件分类: DRAM
英文描述: 64M X 8 DDR DRAM, 0.75 ns, PDSO66
封装: 0.40 INCH, LEAD FREE,PLASTIC, TSOP-66
文件页数: 66/93页
文件大小: 3632K
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
67
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 32:
READ-to-WRITE
Notes:
1. Page remains open.
2. DO n = data-out from column n; DI b = data-in from column b.
3. BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
READ
BST
1
NOP
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T4n
T5n
t
(NOM)
DQSS
DI
b
READ
BST1
NOP
WRITE
NOP
Bank a,
Col n
NOP
T0
T1
T2
T3
T3n
T4
T5
T5n
DO
n
DO
n
t
(NOM)
DQSS
READ
NOP
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T5n
t
(NOM)
DQSS
DI
b
DO
n
NOP
CL = 2.5
CL = 2
T3n
CL = 3
DI
b
BST
1
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Transitioning Data
Don’t Care
DM
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