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参数资料
| 型号： | MT46V32M8P-75ELIT:G |
| 元件分类： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.40 INCH, LEAD FREE,PLASTIC, TSOP-66 |
| 文件页数： | 73/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
73
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 39 on page 75 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 40 on page 76. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 41 on page 76.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
Note that only the data-in pairs that are registered prior to the tWTR period are written
to the internal array, and any subsequent data-in should be masked with DM, as shown
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 46 on page 81 and Figure 47 on page 82. Only the data-in pairs regis-
tered prior to the tWR period are written to the internal array; any subsequent data-in
command, a subsequent command to the same bank cannot be issued until tRP is met.
相关PDF资料 |
PDF描述 |
|---|---|
| MT47H128M4CC-3:B | 128M X 4 DDR DRAM, 0.45 ns, PBGA84 |
| MT47H32M16HR-37EAT:G | 32M X 16 DDR DRAM, 0.5 ns, PBGA84 |
| MT47H64M16BT-3ELIT:A | 64M X 16 DDR DRAM, 0.45 ns, PBGA92 |
| MT47H64M8B6-3ELAT:D | DDR DRAM, PBGA60 |
| MT48H32M16LFCJ-8 | 32M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M8T66ADC1 | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V32M8TG-5B/G | 制造商:Micron Technology Inc 功能描述:DRAM Chip DDR SDRAM 256M-Bit 32Mx8 2.6V 66-Pin TSOP Tray |
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