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| 型号： | NOIH2SM1000S-HHC |
| 厂商： | ON Semiconductor |
| 文件页数： | 42/67页 |
| 文件大小： | 0K |
| 描述： | IC SPACE IMAGE SENSOR 84-JLCC |
| 标准包装： | 1 |
| 系列： | HAS2 |
| 象素大小： | 18µm x 18µm |
| 有源象素阵列： | 1024H x 1024V |
| 电源电压： | 3.3V |
| 类型： | CMOS 成像 |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
| 其它名称： | CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS-ND |
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NOIH2SM1000A
There are three transistors in a pixel. The first one acts as
a switch between the power supply and the photodiode. The
photodiode is equivalent to a capacitor with a
light-controlled current source. The second transistor is a
source follower amplifier, buffering the voltage at the
photodiode/capacitor cathode for connection to the outside
world. The third transistor again is a switch, connecting the
output of the buffer amplifier to an output signal bus.
Activating the reset line drains the charges present on the
pixel’s embedded photodiode capacitor, corresponding to a
black, dark, pre-exposure state, or high voltage. As all pixels
on a row (line) share their reset control lines, the pixels in a
row can only be reset together.
With both reset and select lines disabled the pixel amasses
photo charges on its capacitor, charges generated in the
pixel
output
level
empty well
post-integration output level
full well
photodiode by impinging photons. During this integration
the voltage on the photodiode cathode decreases.
When the select line is asserted the voltage on the
capacitor is connected to the pixel output through the source
follower buffer transistor.
All pixels in a line have their select lines tied together:
upon selection a whole line of pixel output signals is driven
onto the 1024 column buses that lead into the column
amplifiers for further processing and complete or partial
sequential readout to the ADC.
All pixels on a line have their reset lines tied together: the
reset mechanism works on all pixels in a line
simultaneously, no individual or addressed pixel reset (IPR)
is possible.
exposure time
reset
exposure
readout
time
Figure 28. Signal Lifetime in a Three ? transistor Pixel: Reset to Black Level (high voltage),
Photo Charge Integration (dropping voltage), Voltage Readout
Y
(0,0)
X
Figure 29. Front View of Sensor Die: Package Pin 1 is on the Left Side. The Focal Plane Origin is
in the Bottom ? left Corner. Lines (Y) are Scanned Down to Top, Pixels (X) Left to Right
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